Figure 39: Original current waveforms 110
Figure 40: Ipos and Ineg current waveforms 111
Figure 41: Internal external fault binary 111
Figure 42: CT Compensation 112
Figure 43: Permissive Intertripping example 113
Figure 44: Stub Bus protection 114
Figure 45: Six terminal, four junction topology and ring structure 115
Figure 46: Six terminal ring structure with channel allocation 115
Figure 47: Six terminal, four junction topology 116
Figure 48: Autoreclose sequence for a Transient Fault 130
Figure 49: Autoreclose sequence for an evolving or permanent fault 131
Figure 50: Autoreclose sequence for an evolving or permanent fault - single-phase operation 131
Figure 51: Key to logic diagrams 133
Figure 52: Autoreclose System Map - part 1 134
Figure 53: Autoreclose System Map - part 2 135
Figure 54: Autoreclose System Map - part 3 136
Figure 55: Autoreclose System Map - part 4 137
Figure 56: Autoreclose System Map - part 5 138
Figure 57: CB State Monitor logic diagram (Module 1) 148
Figure 58: Circuit Breaker Open logic diagram (Module 3) 149
Figure 59: CB In Service logic diagram (Module 4) 149
Figure 60: Autoreclose OK logic diagram (Module 8) 150
Figure 61: Autoreclose Enable logic diagram (Module 5) 150
Figure 62: Autoreclose Modes Enable logic diagram (Module 9) 152
Figure 63: Force Three-phase Trip logic diagram (Module 10) 152
Figure 64: Autoreclose Initiation logic diagram (Module 11) 154
Figure 65: Autoreclose Trip Test logic diagram (Module 12) 154
Figure 66: Autoreclose initiation by external trip or evolving conditions (Module 13) 155
Figure 67: Protection Reoperation and Evolving Fault logic diagram (Module 20) 156
Figure 68: Fault Memory logic diagram (Module 15) 156
Figure 69: Autoreclose In Progress logic diagram (Module 16) 157
Figure 70: Autoreclose Sequence Counter logic diagram (Module 18) 158
Figure 71: Single-phase Autoreclose Cycle Selection logic diagram (Module 19) 158
Figure 72: Three-phase Autoreclose Cycle Selection logic diagram (Module 21) 159
Figure 73: Dead time Start Enable logic diagram (Module 22) 160
Figure 74: Single-phase Dead Time logic diagram (Module 24) 161
Figure 75: Three-phase Dead Time logic diagram (Module 25) 162
Figure 76: Circuit Breaker Autoclose Logic Diagram (Module 32) 163
Figure 77: Prepare Reclaim Initiation Logic Diagram (Module 34) 164
Figure 78: Reclaim Time logic diagram (Module 35) 164
Table of Figures P54A/B/C/E
xx P54xMED-TM-EN-1