Heathkit H9 - Page 58

address
with the
address
stored in
the
cursor latches
and
they will
output logic 1's
when the
two addresses
are exactly
coincident. These
coincidence gates,
or
comparators,
are
composed
of exclusive NOR
gates,
IC's
508, 503,
and
520. The three
outputs,
+20
coinci-
dence,
+4
coincidence,
and
+12
coincidence.
are
processed
in the
TPU
to
generate
a single
coincidence
signal.
This
coincidence
signal
is used in
the
charac-
ter
generator
circuit
board
to
generate
the
dashed
cursor line
on the
screen. At
the
end of the last
scan
line
of the twelfth
character row,
the screen
refresh
cycle has
been
completed
and the RAM
address
coun-
ters have
accessed,
in sequence,
all
of the active RAM
locations.
As
the vertical
blanking
cycle begins,
the
cursor address
is loaded
from
the cursor latches
into
the
RAM
address
counters.
The RAM
is then
addres-
sed
to the cursor
location
and
data can be read
from
or
written into
that location
in RAM
by the TPU.
If
data
was written
into
the RAM,
the TPU
will
count up
the
RAM
address
counters
to the
next
cursor location.
The new
cursor
address
is then
loaded
and latched
in
the
cursor address
latches.
The
+4
and
+12
scroll
counters
contain
the
start
of
page
or start
of scan information.
The
+12
scroll
counter, IC's
517A,
5178,
and
522
stores the
address
for
one of the
tz
character
rows
of B0
characters. The
+4
scroll counter,
IC506,
stores the
address for
one of
the four
blocks
of
L2
rows
of
20
characters.
fust
before
the
vertical
blanking period
ends, and
the
screen re-
fresh period
begins,
the
scroll,
or start
of
page
infor-
mation
is
loaded
from
the
scroll
counters into
the
RAM
address
counters.
In
long
form,
the
+4
scroll
counter
is
always
held
cleared;
therefore,
the
+4
start
of
page
information
is
always block
number
0. In
short form,
the
+
12
scroll counter
is held
cleared
and
the
start
of
page
information
is
always line
number
0.
The
+20
address
counter
module
does
not have,a
scroll
counter
because
it always
starts
at character 0
regardless
of whether
the mode
is long
or short form.
As
the
scan cycle
begins,
the RAM
address
counters
sequence
through
the
RAM,
starting
with the location
specified by
the
scroll
counters.
Each
of
the
counter
modules
has
a number
of controls
associated
with
it. The
+20
module
has
count-up,
count-down,
load,
and clear inputs
and
two inputs
that
determine
whether
it
cascades into
the
+4
counter
or the
+1.2
counter. The load
input loads
the
outputs
of
the
+20
counter
with the
data
contained in
the
5-bit cursor latch,
IC501
and IC521D.
The
clear
input
sets all five
bits to logic
0.
The
+20
-->
+4
control
connects
the carry
and borrow
outputs
of
the
+20
counter
to the count-up
and count-down
inputs
of
the
+a
counter.
The
+20
--->
+1,2
control
connects
the carry
and borrow
outputs
to
the
count-up and
count-down
inputs
of the
+1.2
counter.
The
+4
module has
count-up,
count-down, load
and
clear inputs
for the RAM
address
counter, and
count-up and
clear inputs for
the
+4
scroll
counter.
There is
also an input
called
"select
scroll
+4"
(Sel
S
+4)
that
determines whether the
output
of
the
cursor
latch
or the
output of the scroll
counter will appear
at
the input
of the RAM
address
counter during the load
cycle. There is also d
=4
-->
+12
input that
connects
the carry and borrow
outputs of the
+4
counter to the
input
of the
+72
counter.
The
+12
module contains
count-up, load, and clear inputs for the RAM address
counter, and count-up and clear inputs for the scroll
counter.
There
is a
+
12 --->
+4
input that
connects
the
carry and borrow outputs
of
the counter to the count-
up and count-down inputs
of
the
+4
RAM address
counter. There are also three select inputs that deter-
mine whether the
RAM
address counter
is loaded
with
cursor information, scroll
information,
or
a bi-
nary 11. The
+12
RAM
address counter,
IC519, is
made from a
+
16
counter,
whose modulus is control-
led by IC515A.
When the output of the counter
reaches
binary 12,
ICs15A
immediately
clears
all four
outputs, effectively
making it
a 0-through-11 counter.
In the
count-down
mode,
as the count
passes
through
0 to 15,
IC525A immediately loads
the
counter with
the binary
11
that
is
generated
by the three select
lines
and the counter
continues to count
down, not
from
15, but from 11.
The
+20
and the
+4
counter modules each contain
an
end-of-line
indicator The
+20
end-of-line
indication
is a binary 19 that is decoded
by
IC525B and IC527A.
A logic 1 at the output of IC527A indicates that the
+20
counter
has reached its highest address. The
+4
end-of-line
indication is a binary 3 that
is
decoded
by
IC511D and appears at the output as a logic 0.
All
three
counter
modules share
a common
cursor latch
enable or cursor
load input.