off. When A1 is
high, a carriage return
is
put
on the
bus; when A2
is high, a
space is
put
on the bus;
and
when both
are high,
a
line
feed is
put
on the bus.
These
characters
are used in
the transmit
page
mode
and during
the erase
cycle.
lC4O7 and
IC408
are latches that are set
by the four
cursor
control keys.
During
the
vertical
scan cycle,
Q401
is turned
on,
enabling the cursor
controls.
When any of the cursor
keys is
pressed,
the
corres-
RAM AND
The RAM
and
Counter circuit board contains
a 1k
x
8
static RAM,
an address decoder, and
a RAM address
counter. Twelve
character lines
can be displayed
on
the
screen. Each line is composed
of
four
blocks
of
zo
characters.
See
Pictorial
+-2. The
RAM address
counter can be broken
down into a
+2O
counter, a
-4
counter,
and a
+12
counter.
During
scan, the
+20
counter, IC502,IC5048, IC50S,
ICs10B,
and IC510C
cascades into the
+4
counter,
IC513,
to access
a block of B0
characters
for
one
character line. The
count-up
signal that moves this
address
counter from
character to
character during
scan comes from
the F
pulse
on
the
character
generator
circuit board. Also
during
scan, the
+
12
address
counter is
counted up by the D
output of the
scan
row
counter
(1C213
on
the
character
generator
circuit board) that drives
the character
generator
row
address.
ThethreeRAM
address
counters
(+20,
+4, +12)
out-
put
a total
of
tt
bits, which is
one more than is re-
quired
to
address the 1k
x
4
RAMs,IC507
and IC516.
IC's
512, 526A, 520D,
and 5278 form
an address
de-
coder that eliminates
unused
address codes and re-
dundancies, and
decodes the 11 bits
down to 10 bits.
The
1k
x
B memory
is made
up
of
two
1k
x
4
memories,
IC507
and
IC516,
whose
10
inputs
are
connected in
parallel.
The
chip select inputs
(eSJ
and the
write enable inputs
(WE)
are
also connected
in
parallel.
When
the write inputs
are high
and the
chip
select inputs
are
low,
eight
bits
of data is
read
from the I/O
ports
of the RAM's.
When the write
ponding
latch is
set
so that
the data can be remem-
bered
until the next TPU
cycle.
During
the TPU
cycle
(vertical
retrace timeJ,
Q40L
turns off so that the data
in
the latches cannot change and confuse the
TPU
circuits.
The 1.2 function
keys at the upper
right
of
the Schema-
tic are single-pole, single-throw;
normally-open
switches
with
pull-up
resistors. These
switches
gen-
erate
logic 1's
and 0's to convey
the
proper
operating
mode
to the TPU
circuits.
COUNTER
COLUNlN
COLUNlN
COLUMN COLUMN
0123
L INE
0
I
2
3
4
5
b
7
8
9
l0
l1
20
CHAR
20
CHAR
20
C
HA R 20 C HA R
PICTORIAL 4-7
inputs are brought low,
data on the bus can be written
into
the
RAM
and latched into
a specific
memory
location that is
determined by the address inputs
when the write inputs
go
high. When
the chip select
inputs
are high, the three
state
I/O
ports
are turned off
and data
can
neither
be
read
from nor written into the
RAM.
The
cursor latches
[IC's
501, 521,D,521C,
5218, and
51BJ
in
the counter modules
store the RAM
address
location
where
the cursor is located;
that is, the
current location
where a character
can be written. As
the RAM
address counters access RAM locations
during
scan, the coincidence
gates
compare the RAM
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