Heathkit H9 - Timing and Processing Unit (TPU)

TIMING
AND PROCESSING
UNIT
(TPU)
The
timing
and
processing
unit is
the central
control-
ler for
all Terminal
functions.
It manages
the
reading,
writing,
and
all data transfers,
scrolling,
and erasing.
It
generates
an
end-of-line bell
signal, a
power
up
reset
routine,
it handles
cursor movements,
and im-
plements
the transmit page
function.
All
of these
ac-
tivities happen
during the vertical
retrace
period.
To visualize
what
is
going
on in the TPU, it
is
helpful
to remember that
there are two distinct modes
of
operation
within the
Terminal.
One
is the scan
cycle
and
the other
is
the
TPU
cycle. During
the scan cycle,
characters are being
displayed on the screen by the
RAM and
counter circuit board
and the character
generator
circuit board. Also,
during this time,
the
TPU
is idle
and there
is
little or no logic activity
on the
TPU
circuit board. The RAM address
counter on the
RAM
and counter
circuit board is, however, being
operated at maximum speed
to
put
characters on the
screen.
As
soon as the vertical
retrace period (TPU
cycle)
begins,
the TPU
begins to
perform
all of the house-
keeping
chores
within the Terminal.
Since the RAM
address
counter is
no longer
being
used to refresh
the
screen,
the TPU
can access it
and use
the RAM for
reading,
writing,
and data
transfers. The
TPU
can also
access
the scroll
counter
and the
cursor latches
to
perform
scrolling
operations
and
cursor movements.
If
data is
coming into
the Terminal
faster
than the TPU
can handle
during the vertical
retrace
period,
the
TPU
interrupts
the
screen refresh
cycle and
starts an
ex-
tended
TPU
cycle. After
the incoming
data has
been
serviced,
screen
refresh
can
start again,
but only at the
start
of the next refresh
cycle. Then, it
will
go
back
and
pick
up where
it left
off.
TPU
TIMING
The
basic TPU
timing
signals
are
generated
by
the A,
B, and
C
outputs of the
scan row
counter,
lCZ1,g
on the
character
generator
circuit
board. These
signals
are
applied
Io IC772
where they
divide
the
vertical
re-
trace
period
into
eight complete
TPU
cycles. Each
cycle
contains
eight
sub-cycles.
Timing Diagram
#3
illustrates
how
the A, B, and
C
outputs and
FIr
gener-
ate a series
of non-overlapping pulses.
These
pulses
are labeled
O thru Z
and each
defines
a specific time
for a
particular
TPU
operation to
occur. The
0, 1,2,
and
7
cycles are
subdivided even further
by ANDing
them
with the
C
[IC710B
&
IC728)
and B
(IC710A
&
IC718C)
outputs
of
the horizontal
character
counter
(1C215
on the
character
generator
circuit
board).
In general,
all reading, writing,
and
data manipula-
tion
operations occur during
the 0
pulse.
See Timing
Diagram
#4.
The 1
pulse
is used
for all
counting
operations.
That is, the RAM
address
counters can be
counted up
and down, the
cursor
can be counted in
any
direction, and
the scroll
counter
can be counted.
The 2
pulse
is used
to check for
scroll coincidence
and
generate
the scroll
command. The
time between
the
3
pulse
and the
6
pulse
is used for
scroll
erase and
erase to
end of line. The 7
pulse
is
used to wrap
up all
of the TPU
operations and
to return
the RAM
counters
to their start
of
page positin-
COUNTER
CONTROLS
During
the
screen refresh
cycle, the
+
2 O RAM
counter
always
cascades into the
+4
counter. The
+12
counter
is
driven
by the
character row
counter on the
character
generator
circuit board.
This
counter setup
is
always the
same regardless
of whether the Terminal
is in
the long form
or short
form
mode.
Long Form
During
retrace,
the
counters are
cascaded
differently
to
alter the format
of
how the
cursor moves
through
the RAM locations.
In long
form,
the cursor moves
from.left
to right
through
all 80 RAM locations
on
a
single
line before
it moves
down to the
next line. This
is
accomplished
by
the
+20
and
+4
counters. The
cursor starts
at the extreme left
end
of the
line
with
both the
+20
and
+4
counters
cleared
(each
reset
to
zero).
The
+20
counter is incremented
by the
C.U.
+20
(count
up
+20)
signal to move
the
cursor to the
right. After
the
+20
counter reaches
19
(11001),
the
next
C.U.
+20
pulse
causes the counter
to count up
to
zero
(00000).
This
generates
a
carry
pulse
that
incre-
ments
the
+4
counter from
0
(00)
to
1
(01).
The
-i20
counter then
accesses
the 20 locations
in
block #t of
the
+4
locations.
When
the
counters
reach 19
and 3,
respectively, the
C.U.
+20
pulse
increments both
counters
to zero. This
causes
a carrv
pulse
from the
+4
counter that
incre-