HP 3457A - Slope Amplifier (U513); DA Compensation (U514 and Q512); A;D Analog Auto-Zero Loop

Since
the
algorithm
that
controls
the
A/D
Integrator
operation
is
zero
seeking,
the
maximum
voltage
present
at
the
output
of
the
integrator
amplifier
US1I2
is
bounded
in
normal
operation.
However,
for
abnormal
conditions,
such
as
an
extreme
overload,
the
integrator
could
enter
a
condition
where
the
output
may
not
be returned
to
zero
in the
alloted
time. To
eliminate
this
condition,
comparator
USI5a
is
utilized
to
detect
both
plus
and
minus
illegal
voltages
(+6.3
volts)
on
the
integrator
and
flag
the
MPU.
This
allows MPU
USOI
to
abort
the
current integration,
disconnect
the
input,
flag
an
overload
condi-
tion
and
provide
extra
time
to
guarantee
a
return
to
zero
for
the
integrator.
Slope Amplifier (U513)
There
are
three
key
components
that
form
the
kernel
of
operation
of
an
integrating
A/D
converter.
These
are
the
current
sources
and
steering
switches
in
the
A/D
Hybrid
USI1,
the
integrator
amplifier,
and
the
comparator.
Of
these,
the
comparator
is
where
the
translation
from
the
analog
domain
to
the
digital
domain
occurs.
Therefore;
the
sensitivity
and
response
time
of
the
comparator
are
critical
to
the
final
A/D performance.
The
comparator
is
located
in A/D hybrid
USI]
and
has
its
input
on
pin
4.
In order to reduce the voltage sensitivity requirements and enhance the available input overdrive of the
comparator,
an
amplifier
(U5S13)
is
inserted
between
the
output
of
the
integrator
amplifier
and
the
comparator
input.
Its
prim
purpose
is
to
amplify
the
smaller
slopes
before
the
comparator
input.
This
offers
improved
resolution
of
slope
zero
crossing
detection.
ce
this
is
its
function,
it’s
generally
referred to as the Slope Amplifier. This amplifier provides an inverting gain of 20.
DA Compensation (U514 and Q512)
The
Multi-Slope
conversion
technique
is
inherently
zero
seeking,
that
is
it
tends
to
keep
the
average
voltage
on
the
integrator
capacitor
(C511)
near
zero.
However;
there
is
still
a
residual
error
which
is
small
but
still
tends
to
bias
the
average
integrator
voltage
to
be
other
than
zero.
This
can
introduce
linearity
errors.
This
residual
error
results
from
the
"charge
memory"
or
dielectric
absorption
(DA)
of
the
integrator capacitor.
To
minimize
the
nonlinearities
caused
by
the
integrator
capacitor
DA,
a
unique
DA COMPENSATION
circuit
has
been
implemented.
The
circuit
is composed
of
USI4a
and
its
gain
network
along
with
FET
switch
Q512.
During
the
run-up
phase
of
the
A/D
conversion
the
DA
Compensation
amplifier
is
connected
to
the
summing
node
of
slope amplifier
US13
through
Q512.
A/D Analog Auto-Zero Loop
Precision
A/D
performance
can
only
be
achieved
by
the
elimination
of
all
potential
error
sources,
For
an
integrator
to
yield
accurate,
repeatable
results,
its
operation
must
be
precisely
controlled.
The
most
critical
aspect
is
being
able
to
provide
a
controlled
starting
and
ending
condition
for
the
integrator.
This
is
the
function
of
the
Analog
Auto-Zero
Loop.
In
this
instrument,
the
Analog
Auto-Zero
Loop
seeks
a
zero
current
condition
for
the
integrator
and
stores
the
necessary
correction
to
force
this
condition.
The
Analog
Auto-Zero
Loop
(AAZ)
is
enabled
between
each
conversion
for
2mS
and
is
also
the
standby
mode
for
the
A/D.
The
Analog
Auto-Zero
Loop
is
composed
of
the
integrator
amplifier
circuitry,
the
slope
amplifier
and
the
hold
circuitry.
The
hold
circuitry
is
formed
by
the
sampling
FET
QS511,
the
hold
capacitor
C512.
hold follower
Q513
and
divider
R519, R520.
Between
readings
FET
switch
QS5I1
is
closed.
This
connects
the
slope
amplifier
(U513)
output
to
the
auto-zero
hold
capacitor
C512.
The
voltage
of
C512
is
followed
(X1
gain)
by
FET
pair
Q513.
The
hold
voltage
at
Q513b,
pin
5
is
then
attenuated
by
the
R519,
R520
divider
(X0.1)
in
order
to
reduce
the
ef-
fects
of
noise
and
hold
capacitor
leak-down
rate
errors.
The
divided
voltage
is
then
applied
as
the
of
f-
set
correction
for
the
integrator
at
its
plus input, Q514,
pin
6.
HP 3457A Multimeter
8-15