HP 3457A - 8-43. Reading information from RAM U506; 8-44. Reading information from RAM U511

© Sets the read/write (R/W) output (USO1 pin 32) high.
©
Sets
the
address
code,
of
the
memory
location
to
be
read,
onto
address
lines
AO
through
Ald.
© Sets address line AI5 high to enable gate U598b.
The
combination
of
the
positive
portion
of
timing
signal
€+a
and
the
high
R/W
signal
causes
a
negative
pulse
at
the
output
of
gate
U598d
(RD).
Simultaneously,
the
positive
portion
of
timing
signal
E+9
and
the
high A1I5 signal cause a negative pulse at the output of US98b (ROM).
The
negative
ROM
signal
activates
the
output
of
ROM
US02
and
causes
a
negative
pulse
at
the
output
of
gate
U596b
to
enable
tri-state
buffer
U517.
The
negative
80
signal
from
U598b
activates
the
output
of
buffer
U5SI7.
The
microprocessor
then
reads
the
information
from
primary
data
bus
"A",
lines
DO
through D7.
8-43. Reading information from RAM U506.
To read information from RAM U506, the microprocessor:
© Sets the read/write (k/W) output (U501, pin 32) high.
©
Sets
the
address
code,
of
the
memory
location
to
be
read,
onto
address
lines
AO
through
Alo.
©
Sets
address
line
All
high
and
lines
Al2
and
Al3
low
to
select
the RAW
output
of
decoder
US13.
© Sets address lines Al4 high and AI5 low to enable decoder US13.
The
low
portion
of
timing
signal
&
(U597b,
pin
4)
activates
the
RAM
output
of
decoder
U513
to
enable
RAM
U506.
The
positive
portion
of
timing
signal
€+a
and
the
high
k/W
signal
pulses
the
output
of
gate
U598d
(RD)
low
to
activate
the
output
of
RAM
US06.
The
microprocessor
then
reads
the
information
from data bus "A", lines DO through D7.
8-44. Reading information from RAM U511.
To read information from RAM USII, the microprocessor:
© Sets the read/write (R/W) output (U501, pin 32) high.
®
Sets
the
address
code,
of
the
memory
location
to
be
read,
onto
address
lines
AO
through
Al0.
©
Sets
address
lines
All
and
Al3
low and
Al2
high
to
select
the
NVRAM
output
of
decoder
US13.
©
Sets
address
lines
Al4
high
and
AIS
low
to
enable
decoder
US13.
The
low
portion
of
timing
signal
E+0
(pin
4
of
gate
U597b)
activates
the
NVRAM
output
of
decoder
U513.
The
NVRAM
signal
is
applied
to
the
emitter
of
Q501
and
causes
a
negative
pulse
at
the
collector
(NVCS)
to
enable
RAM
USII.
The
positive
portion
of
timing
signal
€+0
and
the
high
R/W
signal
pulses
the
output
of
gate
U598d
(RD)
low
to
activate
the
output
of
RAM
USII.
The
microprocessor
then
reads
the
HP 3457A Multimeter
8-19