HP 3457A - 8-45. Writing information to RAM U506; 8-46. Writing to the unprotected section of RAM U511

information from data bus "A", lines DO through D7.
8-45. Writing information to RAM U506.
To store information in RAM U506, the microprocessor:
© Sets the read/write (k/W) output (U5O1, pin 32) low.
*
Sets
the
address
code,
of
the
memory
location
where
the
information
is
to
be
stored,
onto
address
lines
AO
through
A10.
©
Sets
address
line
All
high
and
lines
Al2
and
A13
low
to
select
the
RAM
output
of
decoder
US513.
©
Sets
address
lines
Al4
high
and
A1I5
low
to
enable
decoder
US513.
The
low
portion
of
timing
signal
E+a
(U597b,
pin
4)
activates
the
RAM
output
of
decoder
US13
to
enable
RAM
US06,
The
output
of
U598a
(WR)
is
pulsed
low
by
the
high
portion
of
timing
signal
E+a
and
the
high
R/w
signal
from
inverter
U599e.
This
activates
the
input
of
RAM
U506.
The
microprocessor
then
writes
the
information
to
US06
through
data
bus
"A",
lines
DO
through
D7.
8-46. Writing to the unprotected section of RAM U511.
To
write
to
the
unprotected
section
of
RAM
USI1,
the
microprocesso:
©
Sets
the
read/write
(R/W)
output
(USOL,
pin
32)
low.
©
Sets
the
address
code,
of
the
memory
location
where
the
information
is
to
be
stored,
onto
address
lines
AO
through
A10.
(When
addressing
the
unprotected
section
of
US11,
address
lines
AY
or
A10
or
both
will
be
set
low)
©
Sets
address
lines
All and
A13
low
and
A12
high
to
select
the
NVRAM
output
of
decoder
US513.
© Sets address lines Al4 high and A15 low to enable decoder U513.
The
low
portion
of
timing
signal
E+0
(U597b,
pin
4)
activates
the
NVRAM
output
of
decoder
U513.
The
NVRAM
signal
is
applied
to
the
emitter
of
Q501
and
causes
a
negative
pulse
at
the
collector
(VCS)
to
enable
RAM
USII.
The
output
of
gate
U595d
is
pulsed
low
by
the
positive
portion
of
the
o
timing
sig-
nal
(USOI,
pin 35)
and
the
inverted
r/W
from
inverter
U599e.
This
causes
the
output
of
gate
U59la
(nvuR)
to
go
high.
During
this
time,
a
low
signal
on
address
line
A9
or
ALO
ensures
a
low
output
from
U596a.
The
high
Nvwe
signal
is
applied
to
the
base
of
Q500
through
gate
U594b,
causing
it
to
conduct.
The
low
output
of
Q500
(NVWE)
activates
the
input
of
RAM
USII.
The
microprocessor
then
writes
the
information
to
US1I1
through
data
bus
"A",
lines
DO
through
D7.
8-47. Writing to the protected section of RAM U511.
The
"Write
to
CAL-RAM"
sequence
begins
with
a
CAL
command,
either
from
the
interface
bus
or
from
the
front
panel.
The
microprocessor
is
reset
prior
to
each
calibration
routine
to
insure
that
valid
measurements are obtained.
Calibration
Reset.
Upon
receiving
the
CAL
command,
the
microprocessor
stops
toggling
the
TNoP
signal
and
waits
for the
circuit
to
time
out
and
reset
as
follows:
HP 3457A Multimeter
8-20