HP 3457A - Page 186

¢
A
continually
low
(or
high)
TNOP
signal
applied
to
capacitor
C505
allows
the
input
of
inverter
U591b
to
go
low.
© The high output of U591b and the normally high RESET signal applied to the inputs of gate
U598c cause its output to be held low, disabling the reset to U514 and USIS.
©
Counters
U514
and
USI5
count
the
2
MHz
clock
signal
applied
to
U514,
pin
10.
After
counting
for
524288
usec.
(from
the
last
reset),
the
output
of
U515
pin
9
is
set
high.
©
The
high
output
of
USI5
pin
9
is
applied
to
the
minus
input
of
comparator
U519a
causing
its
output
to
go
low.
The
low
output
from
U519a
is
applied
to
the
plus
input
of
comparator
U519d
causing
its
output
to
go
low.
©
The
low
output
of
U519d
is
coupled through
buffer
U594d
to
the
RESET
input
(USO!
pin
37)
of
the
microprocessor;
to
gate
US98c,
which
causes
its
output
to
go
high
and
reset
count-
ers
U514
and
USIS5
to
zero;
and
to
"flip-flop"
US92b.
Clearing
U592b
sets
its
@
output
high
to
remove
the
low
signal
from
the
CLR
input
of
U592a,
pin
15.
CAL-RAM
Lock
circuit
operation.
The
CAL-RAM
Lock
circuit
protects
the
instruments
calibration
constants
by
preventing
accidental
writing
to
the
protected
(calibration)
sect
ion
of
RAM
USII.
©
After
being
reset,
counters
U514
and
USI5
begin
to
count
the
2
MHz
clock
signal
applied
to
USI4,
pin
10.
©
The
output
of
counter
U514
(pin
3)
is
set
high
4096
Useconds
after
the
circuit
reset.
This
signal
sets
the
"J"
input
of
flip-flop
U592a
high,
enables
gate
US95b,
and
insures
that
the
out-
put
of
gate
U59Id
is
kept
low.
©
The
microprocessor
sets
address
lines
All
and
Al2
high
and
line
Al3
low
to
select
the
CALREO
output
of
decoder
U513.
©
The
negative
portion
of
timing
signal
E+0
(US13,
pin
4)
activates
the
CALRE@
output
of
decoder
U513.
The
CALREO
signal
must
occur
between
4096
and
4100
usec.
after
the
circuit
reset
has
occurred
to
be
valid.
©
The
negative
CALREO
pulse
clocks
the
high
"J"
input
into
flip-flop
U592a
which
sets
output
signal
WWE
low.
The
following
section
titled
CAL-RAM
Write
Operation
explains
how
this
enables
the
write
input
of
RAM
US511.
If
the
TALREQ
signal
is
applied
to
gate
U59Id
while
the
4096
usec.
signal
is
low,
the
output
of
USYld
will
be
set
high,
which
sets
the
output
of
gate
US9Tc
low
to
reser
flip-flop
US92h.
The
low
&
output
of
U5Y2h
clears
flip-flop
US92a
to
“lock”
the
clock input of U592a, the @ output will remain high (locked).
CAL-RAM
Write
operation.
Once
the
CAL-RAM
Lock
circuit
has
been
"unlocked"
(NVE
set
low),
the
microprocessor:
©
Sets
the
address
code,
of
the
memory
location
where
the
information
is
to
be
stored.
onto
address
lines
AO
through
Al0.
(When
writing
(0
the
protected
section
of
US11,
address
lines
AY
and
A10
will
he
set
high.)
©
Sets
address
lines
All
and
Al3
low
and
A12
high
to
select
the
NVRAM
output
of
decoder
US13.
HP 3457A Multimeter
8-21