HP 3575A User Manual

Model
-1515
{
4-l
7.
nr. oL[plll
sr!nal
from
the
preanrplifier
is
applied
to
pin\:0
rIJ
ll Lri
the
Log ,\Iplifier package.
The input
circuir
in tlre
Lor
\nrpliticr
is
protected
by
thc diode_
bridge
li:rriiin_t
rrr't\ork
conrprised
of
AjCRI
through
A-l(
ll-+
The d. op.'raring
poilt
of
the
Log
Amplifier
is
controlled
hr rn .'rrrrnal
itedback
loop
betweenpils
1.1
and
ll
,ri
th.'prikrle
lhe dc
signal
at
pin
l.l is filtcreil
by
a
singlL'pol!'
iliri\._,
ctwork (A3lC:
and associated
cir-
cuitr\
)
rnd
ir
icd
hack
to
pin
ll.
In
order
to obtair
rdeqLrate tilr.ri
! oler
thc entire
frequency
qlectrui),
thc
filter
r,-'spoIs.'
ntist
br'
cllanged
in
accrlrdaItce
rvith
the
input fr.'qu.,nur
.
-Ihis
is lcconrplislted
by nreans
of
transis-
tors
A-iQl tlrr,iulh
,\-t
Q-t
rvhich
are used
to switch
resistors
AlR9.
Rll
:rrLl Ill.t
iI or
out of
thc
R/C filter
network.
Thc
s\\it.hi
g
tr!nsislors
trc
controlled
by two lincs.
FRI
antl FRI r..,
r
rl.( trL, pa
cl
tRFei
I,.N(.\
R \NCl
swit.h.
\or.'
rh.rr th. IiL'.lueucv
range
lines
(FRl
. FRI)
are
dso
-p1'11,.
I
,,
rl..
I,i.c. ,,f
\.tQ.l.
U5
arrtj
eo.
flrc.u
tlansisl(Jr\
rrr' Li\!rJ
1o
slvjt.h-il various
values
of capaci-
tarrce (,\-lCl
rirr,)ugh.\-i(9)at
the
limited
ou(put (pio
ll)
of
the
Log \lrrplirier
The
purpose
of
this
liiteririg
is
to
rrrininire
thr. hirh tiequcncy
noise
couplcil
to the
Level
lranJlJt()r
JnJ tL)ll()\\
iIg PIusc
Detcctor
circuitry.
4-18.
Level
Translator
{A3/44 Og,
09
Schematic
No.
1). The lunir.J
()ulpul
ironr
pin
1l of
the
Log Anrplifier
is
fillereLl
,rnJ
rpplic'J
ro
lhe
Levcl
Trauslatoi
circuit
con-
sisting ol
\-iQ\
rnLl
\-l
Q()
l-he
Level
Translator
is
a
diffr'rc'ntirl
ln)})liii.,r \!hirh
.oDverts
rhe
lcvel
of the
irlcorlrins
\t! il t()
J le\..1
that is
compatible
with the
ent
ilri'r-i,-rup
I r'J
lo!i!
(
hCL
)
Lrsed
iD
the
phase
I)etector
and
assoaialcLl
.irJuirr\.
llte resLlllitlg
outputs
are
two
square
wilvcs
thJr rre .,,luJl
in xl]lplitudc
and
lg0
degrees
out
of
phase.
1he \riuJr.'-\\'!t'e
outputs
lionl
the
Level
Translator
in eirch
lnpul
(hrn
!,I
rre applicd
dircctly.
to
the
phase
Del.
(
r,
,.
. ll.
r.
rt
.
".'i.
lrrr.
J r...t..e,'1
in
prl:r!rrph
J-l
l.
4-19.
Synchronous
Rectifier
and
Summing
Amplifier
lA3/A4 lCA
through
tC6
Schematic
lto.
i). fle tog
outputs
li(inr
pirrs
1.
5
rnd
()
of
thc
Log
Arnplifier
ar!
sunt teJ
11 rh.
!,rni
er oi
e7.
lle logarithntic
signal
at the
..,rlleJt.'r
,,r
0-
i.
Jire.
r
(,,ul,lcll
r,r
t$,r
Ji,,erclliitl
atrtplilt,r.
I e
l.rti.cr.rirl
rrrrplifr..r
irr rlle
upncr p\,rtiul
ol
llr(
\lr<
rtJrr- rl{'+
\)
(liDs
rllc
lpplied
si3nal
urrtl
producc,s
nr o
\quarc-\!.ave
oulputs
tltat
ue equal
irl
amplitud.,
Jnd lt0
dasrees
out
of phase_
The square
waves
rernain
tt arj e\sentlall\
fixed
arnplitude
over the
entirc
dynanric
rcngr'.
The
dillirential
a:rplifier
in
the
lo1y91
porlion
oi lhe
s.hL,rnrtju
(lC4ll)
produces
two iogarithnric
oulpul.
IIrJ,
-r(
(.lLtrl
L
rIlrplit.r,lc
rrrJ
lxUdeJree.,,ut
ot
plrJsc.
All i.'..rr
.'t
rlrc,c
prriotrrlrtiur
ed
sigrralsirc
rpplied
b
the
S\n.hronous
llectifier.
lC5.
In
the
Svnchronou.
lleul iirer.
rl,
.
luJr(-\\!\e
uulput5
l'tult
tlle
Iimit
irrg
itmpli-
ller
{lCl \l rlrerrr:rrclv
jJle.uul
pi,srtive
I:,,i,,g
r,,,1
icgriive
goilg
porrions
oi-
the logarithrnic
signal froin
c.liffer"ential
arrrpliIisr
lI
.tB.
1lri, prtrJu...
p,,.riive
arrJ negarivc
lull-
wavc
rectiiieJ
()urputs
which
are filtercd
by
Cl7 and
C1g
rnd
uornbrr.J
'r
llr(
\uIrrni
g
turrplifjer
tli
o1
r,) proJu.e
a
singie dc r)urpur
voltage
that is
logarithmicaily
pro,
portioni
ro rlie
rnrplitude
oI
rhe
input
signal.
This
ouiput
is
applied
ro the
Panel
Meter
through
the
Function
Section IV
Switching
Assembly
(A8)
and
Output
Filrer
(A9)
in
the
\IlpliruJe
Displll
mode.
"1-10. There
aJe four
adjustments
in
the Synchronous
Rectifier
portion
of the
l,{)g
Converter
Assembly.
The
bias
adjustment.
A3Rl8
(emitter
of
Q7),
is
adjusted for
0 Vdc
at the
collector
of
Q7.
Potentiometer
A3R29 is used
to
balance
the lirniting
amplifier
(lC4A)
to obtain
optimum
symmctry.
Potentiometer
Rj2
adjusts the
gain
of the
Synchronous
Rectifier (lC5)
such that
an
amplitude change
of
70 dB
at
the
input
produces
a 70 dB
change in
the Log
A
(,{3)
or l,()g
B
(A4)
amplitude reading.
The log
offset
adjustment
(R50)
in the
Summing
Amplilier
cicuit
is
adjusted for
a
panel
meter reading
of
+6dBV
with
a
2
V
nns signal
applied
to
rhe
input.
4-21.
Phase
Detector
(A5
Schematic
No. 2).
.+-ll.
Refcr
to the
Furctional
Blu;k Diagram
(Figure
7-l)
and
Schelnatic
No.
I
for
the following
div:ussion.
4-2-1.
Ihe square-wave
outputs from
the
Level Translator
in each
input
channel
are applied
to
the
Limiter circuit
in
tlle
Phase Detector.
The
Liniter circuit
is
comprised
of
two
differential
arnplifiers.
ICIA
and
ICtC.
which
are con-
nected
in
Schnitt
Trigger configurations.
These differential
unplifiers
detect
the
a-\is crossing points
of
the
applied
signals
and
produce
square-wave
outputs
that
are limited
to
approximately
1V
p-p.
The outputs
of
the
Limiter
are
A
which
is in
phase
rvith
the signal
applied
to channel
A. B
which
is i[
phase
wirh the
signal
applied
to channel
B and
B' which
is 180
degrees
out ofphase
with
the
sigrul
applied
to
channel
B.
Note
that the
B signal from
lCt
C is appiiid to
a
third
differential
arnplifier,
ICIB.
The
purpose
oi-lclB
is
to
provide
a
gate
delay
equal
to
that of
the A
channel
Erclusive
OR
gate
(lClC)
so that
both
signals applied
to
the
"Q"
Phase
Detector
(lC2B)
encounter
one
gatsdelay.
.1-1,1.
The
A and B'outputs
from
the
Limiter
are applied
to
the
A channel
and
B
channel
Exclusive
OR
gates (A5lC2C.
ICID).
nrc
purpose
oI rlre
tx.lusive
OR
gates
is ro
provide
irverted
or
flon-inyerted
outputs
in response
to
dc logic
Ievcls.
Note
that the
signal from
chanlel
A is applied
to
o-ne
input
of
the
A channel
Exclusive
OR
gate
whili
a logic
revel
from
rhe liont
panet
PHASE
REFERENCE
siitch
is
applied
to the
other
input. Whenever
/5o1,
inputs
are high
(1)
or low (0),
rhe
output
is low.
If onJy
one
input
is hig"h,
the output
is
high.
For
example,
with
the PHASIE
REFdR-
ENCE
switch
in the
"A''
position,
the logic
input
to
the
A
channel
llxclusive
OR
gate
is high.
The
outpui
of
the
gate
is..therefore,
low
when
the signal
input
is high
mating
it
1-80
degrees
out of phase
with the
sigml
lnput.
Wtn ihe
PHASE
REFERENCE
switch
in the
..-
A,,
position,
the
logic
input
is lorv
and
the
output
is in
phase
with
the signal
input.
The
B channel
Ilxclusive
OR
gate
operates
inlhe
some
nranrler
but is
controlled
by
the logic
output
from
the
"Q"
Phase
Detector (Paragraph
4-30).
4-15.
The outputs
of
the
A channel
and B
channel
Exclusive
OR
gates
are
applied
directly to
two
OR/NOR
4-3

HP 3575A Specifications

General

Brand	HP
Model	3575A
Category	Measuring Instruments
Language	English