Section IV
.1-75.
At th.
strrl ol tllc l])cJsure intervai. the
input ot the
Analog
scction is s$jtciled
to the rnalog
voltage
supplied
by
the instrunrent. l-hc
ldditionrl currqnt
disrupts the balance
irahievcd
in thc auto-zero inlerval.
driving the integrator
olrtpul lway from ths
tLrto-zero equxlibriunr voltage, The
Cornparator
senses this deviatioD
at)d transmits the inlbrma-
tion to thc
Control Logic, rvhich then responds
with
the
propcr
iogic to reestablish
the
zero
level. The tirne required
Ior the Anahg
orLtpilt to return
to
zcro
is accumulxted in
the
Countcr arrrl corresponds 1o the lnalog input.
,l-76.
At
thc eDd of thc rr)casure intcrvai. the count is
transrnitted to
the
Drla
Nlultiplexer where it is converted to
8':l'2-l BCD infonnatiorr.
synclrronizcd wilh the digit and
polarily
strobe and
rppiied
to
the
Display. Polarity
inlor-
lrralion
is aiso trrnsnritled via the BCD
output.
\Vhcn the
measure
intcrval is cor:rplctc and the digits displayed.
a
new
nre!sLlrerlclrt
cycle begins.
4-77.
lhc
Digitrl Prnel
Nlcter
is buill around a 3l/: digit
lnalog
to riigilri convcrtcr
set. AllLll and AllU2.
AllLrl
is an anllog
processor
rvhich
coltains lt bipolar
corilprrelor,
a bipoler ililcglltitrg lmplifier, two MOS-FET
input ullit)'
glin
amplilJcrs. scvcrli
P,cliannel
enl)ancement
mode
unllog switches rnd
thg llcccssary lcvcl shifting
drivers lo
allow tl)c analog
lnd digitrl
processors
to bc
directly intertaccd AllUl
is a
s)nchro
oLrs
digitrl
proccs-
sor thet conrbines
tlr!' cou tirlg.
storlge und dala rnulti-
plcxing
funclions rvillt
lhc rlndom loilic necessarv to
c(lnlrol llrc lirnctions oi
llre aralog
proccssor.
'['hc
digilal
pro0cssor
contains
seventecn stiltis latches for storing tha
-11:
digjts
ol llCD Lhta. overr!nse, underranqc
and
polarily
infornration. Ninc
push-pull
output
buli'ers
provide
the
sign.
digit
strobc and
rnLrltiplcxed
[3CD dltr
outputs.
The
Digitrl Panel NIctcr
provides
I
lull
scale display hrr al
rnalog
input voltage
oi l.999 V. This iull
scale ol
the Prnel
Nlctar
is rloi to be- confused with
instIunreot
full
scale
inclicatiol)s
4-78. l!4easurement Cycle.
The ir,a
digit
lnllog-to-digital
!onvqrtcr scl. AllLll lnri ,\llLll. converls llle !rulog
iI]put !1)itrgc to
a
c()[esponding t-]'l-l BCD output orcc
crch
rrersurL'orcDl
clclc. Pohrit), oveIrrngc
altd
under-
rilnge
inli)rnralion
is llso
dcternrined
oncc each mcasure-
n10nt
cyclc.
Tha nrarsLrrcmcI]t
cyclc
is controllcd b] the
linrc brsc countcr louulcd ir AllLll- l llc lnne base counter
dividcs
the clock
lrecluency
qenelaled
b1
AlfUl into
sampling rnrcrvlls of 61.1,1
pulses
which
constitule
one
n1e!slllL'Dtant cyclc.
Each
ntersurL'rncIll cycle cortsisls of
two-intcrvals llt Juto-zero intcr\'rl rnd r ntclsrlr!' irtcr!ai.
Ol lhc 61.1.1
pulse
rre!surenr.nt cycle, 20,18
pulses
conr-
pris!'
the aulo'rcro
inlerval
and
-lot)b
pulses
romprisc 1he
mcasula intr'rvll.
4-79.
Aulo-Zerc lnterval.
The
purposc
of thc auto-zcro
intcr!al
is to
.slsblisll
an cquilibrium
voltage
wiricir
rcprc\cnls
thc o[lsct illt11)duced
bl lhe drilt ol the analog
s.ction. Rci!r l(r figure
.l-l:
and
.1-l.l
li)!
this discussjon.
'+-E0.
The aulo-zerr) !nd nreasure intervals are controlled
h1'
thc \'leasuLciZcro loglc
(l\liZ.1
originating fror'n ihc timc
.1-l)
Ir'lodel
3575A
base counter in A22U2. A low loglc Jevel on the M/Z lJne
switches
the
inpul ol
the buffer amplificr
to
ground. When
the MiZ logic,
the
Up,iDorvn logic
(U/D)
and the compara-
tor outpul are all l,rw. {he Overrjde section
provides
a
high
output.
This tums off
A2)Q2
and
appiics
-
l2
V lo the
gatc
of
AllQ1. A closedloop systcm
of
integrator
and auto-
zcro amplifie| is ibrrncd by thc opcration ol Al2Ql. The
delay
interval, or overrjde
period,
in iniliating thc closed-
loop
system. aliows the integrator
output to return to the
equilibrjunr vollage ol
lhe
prcvious
mcasurcmcnt cyclc.
.1-81.
The input of thc auto-zcro closed loop syslem
js
the
summing
nodc at the rlcgalive
port
oI the
intcgrrtor
in
Al.+Ul. Thrce currcnts arc summed at this
node. The
bufler anrplificr ilr conjunction
with AllRT l'urnrs a
vollage-1o'currenl
converter
which
supplies currcnt
lo the
integralor
input sLrmminB
nodt.
Vollagc-to-cr.urcnt
convcr-
sion is als,l
perli)rllred
by
thc luto-zero .rnrplilier irt
conjurclior willl
A2lR()
and the rctarcI]cc
voltrgc
iri
conjunclion with r\llR-l end AllR5. Thcsc rre' th.' otlicr
tlvo cLlrr.nts
summed rl
the
summing
node.
Sinc.' the
bul-lcr lnlpli,lcr input is
grournded,
thc
.unen1
sullplrcJ 1o
the rntrqraior sunrming nodc is nrinor. The lulozcrr
rmpliller
cu[ent alld the
referencc currcnt nre the rnijor
currer]ls
llowing nrto lhe inlellrlioI slrmming
ntrde. The
relcrcncc
currcrt is
pulscd
at x 50'i duty cyclc
(.1
clock
cycles or
aod
,1
clock c)'cl.s
o1'l-) b; thc Ur'D logic
gcncratcd
in thc control logic
portion
ol A2lUl. The
output
of the
jllegrat()r
in llie
closed-lo,.rp
s\'slcnr s.cks to
rllaiIr ln !,(luilibriunr voltlgc.
Equilibrium
occurswh!,n thc
sum ol_
lhg avcll-r!e'currcnts ilt
lllL'irtagrrlor
sunmlillg
node
cquals zcro.
At erluilihriunr. 1hc cu,rcnt tlrroLrgh AllRtr
rvill
bc consllnl ll]d crlull to hall thc
rctir.I]aL-
curcrt.
Thcse lwo
cuncllts
opposc
ciich
()lhcr
irl lhc i tag[llor
sunrming nodc li)r
r
net resull ol lcro.
.+-81.
Thc cquillblium
voltlgt'
is storcd or) r'lpilcitor
Al2C-1. This voltagc
is the dc
olt\e1
introduced by the
rnalo.q
section.
During
tlic
lbllowing measure
illlerval.
the
cquiiibrium voltrse
storcd on AllCS is applicd to the
integralor
sunnDinI
r]odc where
jt
nullitles
tl'rc olTsel.
4-83. lVleasure
lnterval,
Rciir
1()
Figure
.l-12
and
.+-14
for
this discussiorl. Following tllc
2048
pulsc
auto-zero irtcrvill.
the
M/Z logic
gocs
high to bcgin thc nreasure intr'r'val. The
MiZ logic slvitches the buflcr antpliticr input fiom
ground
to the
arlalog
voltage
supplied 1o the
panel
meter.
I1 rlso
opens
the closcd-loop system of
j
aegrator aDd aulGzcro
amplilier. Thc
voltase-to-cu
rren
t converter contpris!'d of
the buffer amplificr and A22R7 supplics a currcnt to the
illtcgretor
summing node
gederated
by the anal(ig input
voltlge.
This additional current flowing into
thc integrator
summing nodc disrupts thc balancc
achicved during the
preceding
auto-zero inlcrval. The result is
the integrator
oritput
is drivcn away from thc
equilibriunl voltagc
main-
tained as a reference on
A22C3.
The
greater
the
analog
irlput voltage,
lh9
greater
tlre integrator output deviates
from
the equilibrium voltage.
Al2CRl
in
parallel
with
the
lntegrator
capacitor A22C2
protccts
thc intcgrator
against
large
positive
analog input voltages.
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