trlodel
-15
75 A
Section IV
-|
AUTO
ZERO MODE
\-F-Fri^F
r !rlrraE )
CUIP!I-
\.
/
8.
I\IEASURE
I\,1O D E
Figure
4-'13.
Analog and
Digiral
Timing.
-1-8.1.
The
ctllrparalor
ol Alltll
is a diftererrli!i arnplitier
rvhich
compares tlie
integrrlor
outpul lo the
t'cluilibrJLrrrr
voltagc
stored on AllC,l. I'he complrltor trlnsrnits by
logic
Ievels 10 rhc control logic oi AllUl. 1h!' slll!' of thc
inlegr0tor outpul with
respecl 1o
lhL'equilibliunr volllge. A
high logic lcvcl iDdicates an inlcgraror output
grcetcr
thJn
equiljbrium:
a
low iogic
level indiclte: lr) integrrtor oulpul
lr-'ss than equilibriun). l hc c,rntlol Iogic
uttempts
to
recstlblish lllc slsl!'nr a(llrilibrunr hv
usrrtg
one of tuo Ll
'D
lLrgrc
duly elclcs dulirrg lh!'nl.asLl,. inlcr\rl.
Tha
dLrt)
clclt
Lrscd
depends or
llre cornprrirol
oulpur in lhe.lr)ak
cyclc
prcct'ding
.'r!h rlLrl] c).1c. [:igur..l-]-l
:ho*: thc
linrins ot thrso dLrl) eycics un,.l lhalt cllc.r
()n
th.
ifte!rltor
ou tput.
-1
ll