Table 8-13. Control Word at Primary Address (U3 and U4) (continued)
Bit
Mnemonic
Bit 2
GAINX2
Bit 3 VTRIG-POL
Bit 4 LSAMPLE
Bit 5 LADCEN
State
Description
Turns on X2 log expand amplifier.
1
A16U43 turned on. (5 dB/div or 1 dB/div scale)
0
A16U43 turned off. (10
dB/div,
2 dB/div, or linear scale)
Controls digital video trigger polarity.
1
Negative-edge video trigger.
0
Positive-edge video trigger.
Enables sample detection mode.
1
Sample detection mode disabled.
0
Sample detection mode enabled.
Enables FADC memory for
‘Lwrites”.
(Toggled in conjunction with bit 0.)
Bit 6
Bit 7
Bit 8
Bit 9
LLOADADDR
LLOADPOST
LVTRIG-EN
LREADCLK
1
Disables FADC memory for “writes”.
0
Enables FADC memory for “writes”.
Enables load address counter.
1
“Writes” to the address counter disabled.
0
“Writes” to the address counter enabled.
Enables load post-trigger counter.
1
“Writes” to the post-trigger counter disabled.
0
“Writes” to the post-trigger counter enabled.
Enables digital video trigger on A16.
1
Digital video trigger disabled.
0
Digital video trigger enabled.
Clocks counters during “read” mode. Used to load
post-trigger counter or address counter. Also used to
post-increment address counter following memory “reads”.
1
Read clock disabled.
0
Read clock enabled.
ADC/lnterface
Section 8-35
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