Table 1. A3 Digital Storage Mnemonic Table (continued)
Mnemonic
CRT DSBL
AX
AY
DIM
DOTEN
FO - Fll
FCO - FC3
PSO - PS3
FREQ ZERC
FS
FSOUT
FSZ
HLDX
HLDY
HOLD
HSWP
tCLK
INSELA
INSELB
INTG
[NTR
tOBO
[OB15
[OC
KSO - KS3
JO-
L7
LADC
.BLANK
,CLK
LCLRSA
LDCHAR
LDEXP
LDMEN
LDMAR
JDMDR
Description
CRT Disable Control
Delta X Position
Delta Y Position
Dim CRT Display Control
Dot Enable
Function Bus Bits 0 through 11
Data Manipulator Function Control Bits
C
thru 3
1/0 Port Selection Bits 0 through 3
Frequency Zero Control
Fast Sweep Mode
Fast Sweep Output
Fast Sweep Z Axis
Hold X Position (Sample and Hold Control
Hold Y Position (Sample and Hold Control
Track and Hold Control
HIGH = Sweeping
Indicator Clock (Front-Panel LEDs)
Input Selection Bit A
Enput Selection Bit B
Integrator Control
tnterrupt
instrument Bus Data Bits 0 through 15
L/0 Port Input/Output Control
Constant Selection Bits 0 through 3
jink State Bus Bits 0 through 7
,0W = Enable ADC Output
,0W= Blanking Control
nverted CLK
LOW = Clear Stroke Address
Load Character Register
joad Expand Register
Data Manipulator Output Enable
.>oad Memory Address Register
joad Memory Data Register
Mnemonii
NSO - NS7
0S10
OS20-1
DS20-2
PENLIFT
=0S
QSO - QS3
R.0 - R 11
RBWA
RBWB
RBWC
RBWD
REC CAL
IEC ZERO
IMO - RM2
RSEN
RSHS
30 - Sll
30-S7
5G10
5G20-1
SG20-2
»MPL
JTROK8
SWITCH
«WA
^BWB
/BWC
/BWD
/IDEO
C
{
r
Description
Next State Bus Bits 0 through 7
Offset Gain Controls
Recorder PENLIFT Control
Sign of ALU Results
Qualifier Selection Bits 0 through 3
Ram Bus Bits 0 through 11
Resolution Bandwidth Controls
Recorder Calibrate
lecorder Zero
lam Register Select Bits 0 through 2
Reset Peak Detectors Enable
Reset High Sweep
Source Bus Bits 0 through 11
State Bus Bits 0 through 7
Step Gain Controls
■ample
Itroke 8 of Current Character
Jp/Down Converter Control
Ideo Bandwidth Controls
/ideo Signal
lorizontal Signal to CRT
Vertical Signal to CRT
ntensity Signal to CRT
2 IF Overall Block Diagram
To Next Page
Loading...
