IF Overall Block Diagram
Table 1. A3 Digital Storage Mnemonic
Table
Mnemonic
Description Mnemonic
Description
18.4MHZ LO
[MHZ
21.4MHZ
3 MHZ
A LOG
AO - All
AlOdB
A20dB
A2dB
A4dB
A.8dB
AJDRO
ADR3
kUX BLANK
<OJX Z
WdB
BLOG
BO - Bll
BLO - BL6
BLINK
BRIGHT
BS
BWS
BW63
BW68
BW7
2HAR
3LK
18.4 MHz Local Oscillator Signal
1 MHz ADC Clock
21.4 MHz IF Signal
3 MHz IF Signal
Log Expand Control
Accumulator Bus Bits 0 through 11
Attenuation Controls
Instrument Bus Address Bits 0 through 3
Auxiliary Blanking Output
Auxiliary Z Axis Output
Attenuation Control
Log Expand Control
Digital Storage Bus Data Bits 0 through 11
Branch Length Bus Bits 0 through 6
Blink CRT Display Control
Bright CRT Display Control
Block Switch Control
Bandwidth Controls
Memory Chip Enable
Character Mode Display Control
8 MHz System Clock
LDRMP
LDSR
LDX
LDY
LFSEN
LG 10
LG20
LGCLK
LGX
LGY
LINCRSA
LINTG
LL
LLGBLANK
LLL
LMEMEN
Log/Linear Control
LQ
LROMEN
LRSTO
LRTN
LRTRC
LT10
LTON
LTSTA
LTSTB
LWRITE
LZERO
MA0-MA11
Load Ramp Register
LOW = Digital Storage Ready
Load X Position Register
Load Y Position Register
LOW = Fast Sweep Enable
Linear Gain Controls
200 kHz Line Generator Clock
Line Generator Horizontal Signal
Line Generator Vertical Signal
Increment Stroke Address
LOW = Integrator Control
Long Line
LOW = Line Generator Blanking Control
LOW = Long Line
LOW = Enable Memory Output
LOW = Selected Qualifier
LOW = ROM Enable
LOW = Reset Trigger Occurred
LOW = Enable Interrupt Return
LOW = Retrace Signal
LOW= IF-Display Section 1/0 Strobe
LOW = Turn On
LOW = Input Test A Data
LOW = Input Test B Data
Memory Write Control
Output of Zero Check on ALU Result
Memory Address Bus Bits 0 through 11
IF Overall Block Diagram
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