Model 8903B
Service
SERVICE SHEET 6-A4 Output Amplifier/Voltmeter Assembly (Detector
and
Meter
Cir-
cuits)
PRINCIPLES
OF
OPERATION
General
This portion of the Output Amplifier/Voltmeter (A4) contains the Output RMS/Average/Quasi-peak Detector,
Output Overload Detector, and
SINAD
meter circuitry.
Output RMS/Average/Quasi-peak Detector
The circuits on the upper half of the schematic diagram form the Output RMS/Average/Quasi-peak Detector
referred to in the block diagrams. When used as a true rms converter, the Output RMS/Average/Quasi-peak
Detector converts the ac input signal into a dc voltage equal
to
the root mean square (rms) of the input level. The
circuits form an analog computer which converts the ac signal to its dc
rms
equivalent by
a
method called implicit
conversion. The analog computer performs logging, antilogging, squaring, averaging, and dividing mathematical
functions. When used
as
an average-responding converter, the Output RMS/Average/Quasi-peak Detector converts
the ac input signal
into
a dc voltage equal to the absolute average (that is, full-wave rectified and filtered) of the
input level but calibrated
to
the
rms
value of a sine wave. When used as a quasi-peak converter, the Output
detector converts the ac signal to
its
dc quasi-peak equivalent. This type of detector has
a
fast rise time coupled
with a slow decay time constant which ncapturesn impulses
or
other signals with a high crest factor (noise
or
repetitive signal bursts).
Refer to Figure 8B-33, which is
a
simplified diagram of the circuit showing only the components which produce
the
rms
conversion. Since the log-antilog circuit cannot operate on a bi-directional signal, the input is full-wave
rectified. Full-wave rectification is accomplished by half-wave rectifying (and inverting) the input, then summing
the rectified current with a current proportional to the input voltage but weighted by one half. U5, R55, R62, and
CRll perform the half-wave rectification. The rectified signal produces
a
current
(I1
)
in R71 which
is
summed
with the current
(I2)
in R70
at
the inverting
(-)
input to U4. R70 is twice the resistance of R71.
U4, Q2A, and
Q1A
form the Log Amplifier. The full-wave-rectified current
(I3
=
I,
+
I,
)
flows through transistors
Q2A and
Q1A
and into the output of U4. (Q2A
is
a common-base stage; Q1A
is
configured
as
a diode.) The
current
(I3)
through Q2A and Q1A produces a voltage across each base-emitter junction proportional
to
the log
of the current. The sum of the
two
base-emitter voltages
(V,
)
is
the sum of
two
nearly identical logarithms and is
proportional
to
the log of the square of the current (log
I,
)
and hence the log of the square of the input voltage
(log
VI,
).
(The identity used here
is:
log
I
+
log
I
=
log
(I
x
I)
=
log
I2
.)
Now consider the operation of the
Filter
Amplifier, which also functions
as
an
antilog circuit. The collector current
(I,)
of Q1B is filtered by U3 and the associated resistors and capacitors (R90, R91, R92, R94, C53, and C56).
The dc component of this current
flows
through R90, R91, and R92
and
produces a voltage which, when buffered
by U2, is the output
(VOUT)
of
the circuit. (The effects of R93 and R95
in
the schematic are being momentarily
ignored.) U3 also holds the collector of Q1B at ground potential to establish the offset of the output at
OV.
The
collector current
(I,
)
of Q2B is generated by the output voltage
(V0UT
),
which appears across R98.
U12
holds
the collector
of
Q2B and one end of R98 at ground potential.
The voltage across the base-emitter junctions
of
Q1B
and Q2B
is
proportional to the log of their respective
collector currents. The sum
of
the
two
base-emitter voltages
(V,
)
is
proportional
to
the log of the product of the
two
collector currents
(I,
x
I,).
Since the sum of the base-emitter voltages of Q1B and Q2B equals the sum
of
Q1A
and Q2A, the products of the respective collector currents are equal
(I,
=
I,
x
I,
).
Recalling that the dc
component of
I,
produced the output voltage
(VOUT)
and
that
the output voltage produced
I,,
it
is evident that
the output voltage is proportional
to
the square root of the product of
I,
and
I,
and thus
is
proportional to the
input voltage
(VI,),
which has been squared, filtered (to obtain the mean level), and the square root obtained.
Refer now to the schematic diagram, Figure 8B-117
(SS6).
The switches of U23 and U25 control whether the
detector functions as a true rms, average or quasi-peak responding converter. The switch modes are cataloged in
Table 8B-27.
8B-42
rev.20JUN87
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