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Table 3. DMA I/O address map (continued)

Address (hex) Description Bits Byte pointer

0083 Channel 1, page table address register 00 – 07

0087 Channel 0, page table address register 00 – 07

0089 Channel 6, page table address register 00 – 07

008A Channel 7, page table address register 00 – 07

008B Channel 5, page table address register 00 – 07

008F Channel 4, page table address/refresh

00 – 07

00C0 Channel 4, memory address register 00 – 15 Yes

00C2 Channel 4, transfer count register 00 – 15 Yes

00C4 Channel 5, memory address register 00 – 15 Yes

00C6 Channel 5, transfer count register 00 – 15 Yes

00C8 Channel 6, memory address register 00 – 15 Yes

00CA Channel 6, transfer count register 00 – 15 Yes

00CC Channel 7, memory address register 00 – 15 Yes

00CE Channel 7, transfer count register 00 – 15 Yes

00D0 Channels 4–7, read status/write command

00 – 07

00D2 Channels 4–7, write request register 00 – 02

00D4 Channels 4–7, write single mask register bit 00 – 02

00D6 Channels 4–7, mode register (write) 00 – 07

00D8 Channels 4–7, clear byte pointer (write) N/A

00DA Channels 4–7, master clear (write)/temp

(read)

00 – 07

00DC Channels 4–7, clear mask register (write) 00 – 03

00DE Channels 4–7, write all mask register bits 00 – 03

00DF Channels 5–7, 8- or 16-bit mode select 00 – 07

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