Chapter 2. The POWER7 processor 25
2.3 Using POWER7 features
This section describes several features of POWER7 that can affect performance, including
page sizes, cache sharing, SMT priorities, and others.
2.3.1 Page sizes (4 KB, 64 KB, 16 MB, and 16 GB)
The virtual address space of a program is divided into segments. The size of each segment
can be either 256 MB or 1 TB on a Power System. The virtual address space can also consist
of a mix of these segment sizes. The segments are again divided into units, called
pages.
Similarly, the physical memory on the system is divided into page size units called
page
frames
. The role of the Virtual Memory Manager (VMM) is to manage the allocation of real
memory page frames, and to manage virtual memory page references (which is always larger
than the available real memory). The VMM must minimize the total processor time, disk
bandwidth price, and response time to handle the virtual memory page faults. IBM Power
Architecture provides support for multiple virtual memory page sizes, which provides
performance benefits to an application because of hardware efficiencies that are associated
with larger page sizes.
1,2
The POWER5+ and later processor chips support four virtual memory page sizes: 4 KB, 64
KB, 16 MB, and 16 GB. The POWER6 processor also supports using 64 KB pages inside
segments along with a base page size of 4 KB.
3
The 16 GB pages can be used only within
1 TB segments.
Large pages provide multiple technical advantages:
4
Reduced Page Faults and Translation Lookaside Buffer (TLB) Misses: A single large page
that is being constantly referenced remains in memory. This feature eliminates the
possibility of several small pages often being swapped out.
Unhindered Data Prefetching: A large page enables unhindered data prefetch (which is
constrained by page boundaries).
Increased TLB Reach: This feature saves space in the TLB by holding one translation
entry instead of n entries, which increases the amount of memory that can be accessed by
an application without incurring hardware translation delays.
Increased ERAT Reach: The ERAT on Power is a first level and fully associative translation
cache that can go directly from effective to real address. Large pages also improve the
efficiency and coverage of this translation cache as well.
Large segments (1 TB) also provide reduced Segment Lookaside Buffer (SLB) misses, and
increases the reach of the SLB. The SLB is a cache of the most recently used Effective to
Virtual Segment translations.
1
Power ISA Version 2.06 Revision B, available at:
http://power.org/wp-content/uploads/2012/07/PowerISA_V2.06B_V2_PUBLIC.pdf
2
What’s New in the Server Environment of Power ISA v2.06, a white paper from Power.org, available at:
https://www.power.org/documentation/whats-new-in-the-server-environment-of-power-isa-v2-06/
(registration required)
3
Multiple page size support, available at:
http://publib.boulder.ibm.com/infocenter/aix/v7r1/index.jsp?topic=/com.ibm.aix.prftungd/doc/prftungd
/multiple_page_size_support.htm
4
What’s New in the Server Environment of Power ISA v2.06, a white paper from Power.org, available at:
https://www.power.org/documentation/whats-new-in-the-server-environment-of-power-isa-v2-06/
(registration required)
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