36 POWER7 and POWER7+ Optimization and Tuning Guide
SMT thread priority levels
Table 2-7 lists various SMT thread priority levels that are supported in the Power Architecture.
The level at which code can set the SMT priority level to is controlled by the privilege level that
the code is running at (such as problem-state versus supervisor level). For example, code that
is running in problem-state cannot set the SMT priority level to High. However, AIX provides a
system call interface that allows the SMT priority level to be set to any level other than the
ones restricted to hypervisor code.
Table 2-7 SMT thread priority levels for POWER5, 6, and 7
28, 29
Various methods for setting the SMT priority level are described in “APIs” on page 37.
AIX kernel usage of SMT thread priority and effects
The AIX kernel is optimized to take advantage of SMT thread priority by lowering the SMT
thread priority in select code paths, such as when spinning in the wait process. When the
kernel modifies the SMT thread priority and execution is returned to a process-thread, the
kernel sets the SMT thread priority back to Medium or the level that is specified by the
process-thread using an AIX system call that modified the SMT thread priority (see “APIs” on
page 37).
Where to use
SMT thread priority can be used to improve the performance of a workload by lowering the
SMT thread priority that is being used on an SMT thread that is running a particular
process-thread when:
The thread is waiting on a lock
The thread is waiting on an event, such as the completion of an IO event
Alternatively, process-threads that are performance sensitive can maximize their performance
by ensuring that the SMT thread priority level is set to an elevated level.
SMT thread priority level Minimum privilege that is required to set level in
POWER5, POWER6, and POWER7
Thread shutoff
(read only; set by disabling thread)
Hypervisor
Very low Supervisor
Low Problem-state
Medium low Problem-state
Medium Problem-state
Medium high Supervisor
High Supervisor
Very high Hypervisor
28
Setting Very Low SMT priority requires only the Problem-State privilege on POWER7+ processors. The required
privilege to set a particular SMT thread priority level is associated with the physical processor implementation that
the LPAR is running on, and not the processor compatible mode. Therefore, setting Very Low SMT priority only
requires user level privilege on POWER7+ processors, even when running in P6-, P6+-, or P7-compatible modes.
29
Power ISA Version 2.06 Revision B, available at:
http://power.org/wp-content/uploads/2012/07/PowerISA_V2.06B_V2_PUBLIC.pdf
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