AP29000
Connecting C166 and C500 Microcontroller to CAN
Ways of handling the SAE 81C90/91 and the CAN Module on the C167CR / C515C
Application Note 59 V 1.0, 2004-02
• Now the baudrate is configured via the registers BRPR, BL1, and BL2. The values
for the parameters TSEG1, TSEG2, SJW in the registers BL1 and BL2 as well as
the value of the baudrate prescaler in the register BRPR are equivalent to those in
the Bit Timing Register of the C167CR (not C515C because of the missing
prescaler!) and can also be calculated the same way (see section 5.3). If the input
signal is evaluated digitally (only RX0 used), bit DI in BL2 has to be set. If the input
signal is applied to the input comparator (RX0 and RX1 used), DI has to be cleared.
According to the CAN specification, the Speed Mode bit SM should be cleared (only
the recessive to dominant edge is used for synchronization). Example for 125 kBit/s
(81C90/91 external clock = 20 MHz):
BRPR = 0x04; /* load BRPR (Addr. 03h) */
BL1 = 0x49; /* load BL1 (Addr. 00h) */
BL2 = 0x41; /* load BL2, Digital Input (Addr. 01h) */
/* 0 1 0 0 1 0 0 1 <BL1 BL2> 0 1 0 0 0 0 0 1 */
/* S TSEG2 TSEG1 I D - - - S SJW */
/* A P I M */
/* M O */
/* L */
• In the Interrupt Mask Register IMSK, bit ERI is set to globally enable interrupts to the
host controller generated by incoming messages. Other interrupts (on completed
transmissions, on reception of a Remote Frame, on entering the bus-off state etc.)
can be enabled as well if desired. Afterwards, in the Receive Interrupt Registers
RIMR1 and RIMR2 the message objects that shall generate an interrupt on the
reception of a message have to be specified individually (here: message objects 1 to
5).
IMSK = 0x01; /* (Addr. 0Ah) interrupt on reception */
/* 0 0 0 0 0 0 0 1 */
/*ETCI EEPI EBOI EWUPI ERFI EWLI ETI ERI */
RIMR1 = 0x3E; /* (Addr. 06h) recv. int. for MO 1 to 5 */
RIMR2 = 0x00; /* (Addr. 07h) */
/* 0 0 1 1 1 1 1 0 <RIMR1 RIMR2> 0 0 0 0 0 0 0 0 */
/* Messages */
/* 7 6 5 4 3 2 1 0 1 1 1 1 1 1 9 8 */
/* 5 4 3 2 1 0 */
• The Output Control Register, which specifies the connection to the physical layer,
has to be configured according to the application. In this example, it is configured to
output a low level at pin TX0 if a dominant bit is to be sent. It outputs a high level, if
the bit to be sent is recessive.
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