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Infineon C166 Series - Handling SAE 81 C90;91 Operations: Initialization & Interrupts

Infineon C166 Series
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AP29000
Connecting C166 and C500 Microcontroller to CAN
Ways of handling the SAE 81C90/91 and the CAN Module on the C167CR / C515C
Application Note 58 V 1.0, 2004-02
General hints concerning the interrupt handling:
1. When resetting INTPND, also the corresponding value in the INTID in the interrupt
register is cleared. If further interrupts are pending, the interrupt with the next
highest priority will appear in INTID. If no more interrupt is pending, INTID will get
00h. A CAN interrupt service routine must not be left until INTID has the value 00h.
Otherwise the interrupt line to the stays active and no further interrupt generation
from the CAN module to the CPU occurs.
2. Please note that reading the status partition (= high byte) of the Control/Status
Register of the C167CR will clear the Status Change INTID in the Interrupt Register.
Also note that this also happens when reading the whole 16-bit Control/Status
Register because this word access also reads the status partition of this register. If
you want to read the control partition without the clearing of the Status Change
INTID, use byte access to the low byte of the Control/Status Register. - Reading the
Status Register in the C515C has the same effect of clearing the Status Change
INTID.
3. The Interrupt with the lowest INTID has the highest priority. If an interrupt with a
higher priority occurs, before a pending interrupt with lower priority is serviced, the
INTID is updated accordingly. So the servicing of the lower priority interrupt has to
be postponed.
6.5 Ways of Handling the SAE 81C90/91
6.5.1 The Initialization of the SAE 81C90/91
The initialization starts with setting both the bits IM and RES in the Mode/Status
Register MOD. The Control Register CTRL activates some special functions, but
clearing it to 00h is fine for the first approach. Then also the Interrupt Register is
cleared.
MOD = 0x03; /* load MOD (Addr. 10h) */
/* 0 0 0 0 0 0 1 1 */
/* ADE RS TC TWL RWL BS RES IM */
CTRL = 0x00; /* clear CTRL (Addr. 12h) */
/* 0 0 0 0 0 0 0 0 */
/* RX TST TSP1 TSP0 TSOV SME TCE MM */
INT = 0x00; /* clear INT (Addr. 11h) */
/* 0 0 0 0 0 0 0 0 */
/* TCI EPI BOI WUPI RFI WLI TI RI */

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