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General| Architecture | 16-bit |
|---|---|
| CPU Core | C166 |
| Data Bus Width | 16-bit |
| Address Bus Width | 24-bit |
| Maximum Addressable Memory | 16 MB |
| Instruction Set Architecture | C166 |
| Clock Speed | Up to 40 MHz |
| I/O Pins | Varies |
| Timers | Multiple timers/counters with various modes |
| Communication Interfaces | UART, SPI, I2C, CAN |
| PWM | Yes |
| Interrupt Controller | Yes |
| Operating Voltage | 3.3V or 5V |
| Operating Temperature | -40°C to +85°C or +125°C |
Lists and defines abbreviations and symbols used throughout the application note.
Explains vehicle bus system requirements like data rate, integrity, and data sharing.
Discusses CAN protocol definition by Bosch and its market adoption.
Covers CAN's asynchronous serial bus, logic, and physical layer.
Explains message identifiers and CSMA/CD with NDA for bus access.
Details Standard/Extended Data/Remote Frames and Error Frames.
Covers nominal bit time, error detection (CRC, ACK, Bit, Stuff), and error states.
Differentiates between Standard/Extended and Basic/Full CAN implementations.
Provides an overview of Infineon's C500 and C166 microcontroller families.
Describes functional blocks, registers, and addressing of the CAN module.
Details the features, functional blocks, and registers of the SAE 81C90/91.
Shows hardware connections and notes for C167CR/C515C with a CAN transceiver.
Illustrates SAB 80C166 connection using the parallel interface of SAE 81C90.
Demonstrates serial connection of C511/C513 microcontrollers using SAE 81C91.
Proposes SUB-D connectors and pin usage for CAN bus cables.
Explains register access via names and addresses for C167CR and C515C.
Details calculations and programming for TSEG1, TSEG2, SJW, and BRP.
Covers initialization, data frame, and remote frame transmission.
Explains SAE 81C90/91 initialization, interrupt handling, and register configuration.
Describes Basic-CAN feature with MO 15 and Monitor Mode of SAE 81C90/91.
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