Integra DHC-9.9

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -32
BLOCK DIAGRAM
PIN CONFIGURATION
U8031: S29GL128N (128 Mbit Flash Memory)
TX-SR876/SA876
V
CC
V
SS
WE#
WP#/ACC
CE#
OE#
STB
STB
RY / BY#
RESET#
V
IO
BYTE#
S TATE
CONTROL
COMMAND
REGISTER
PROGRAM VOLTAGE
GENERATOR
ERASE VOLTAGE
GENERATOR
SELECTER SWITCH
INPUT/OUTPUT
BUFFER
DATA
LATCH
CHIP ENABLE
OUTPUT ENABLE
LOGIC
Y-DECODER
X-DECODER
Y-GATE
CELL MATRIX
ADDRESS LATCH
TIMER
Vcc DETECT CIRCUIT
A0-A22
DQ15-DQ0(A1)
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
25
26
27
28
9
10
11
12
13
14
15
56
41
55
54
53
52
51
50
49
48
47
46
45
44
43
42
33
40
39
38
37
36
35
34
29
32
31
30
NC
A18
A22
A15
A14
A13
A12
A10
A11
A9
A8
A19
A20
A21
WE#
RESET#
WP#/ACC
RY/BY#
A1
A17
A7
A6
A5
A4
A3
A2
NC
NC
A16
DQ2
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
A0
NC
NC
NC
OE#
V
SS
V
IO
CE#
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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