EasyManuals Logo

Intel 80286 User Manual

Intel 80286
515 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #117 background imageLoading...
Page #117 background image
MEMORY MANAGEMENT AND VIRTUAL ADDRESSING
r
,J
I
C
ONE
SEGMENT
OF THE
,
,
TASKS
RESERVED-ZERO
LOCAL
1-
(private)
1.
BASE
23-16
ADDRESS
RESERVED-ZERO
SPACE
1-
BASE
15-0
I
BASE"_'6
LIMIT
'5-0
BASE,S_O
LIMIT '5-0
LDT
DESCRIPTOR
IN
THE
GDT
IN MEMORY
DESCRIPTOR SEGMENT
TABLES
IN
IN
RAM RAM
f-,
Figure 6-5. LOT Descriptor
6.5
SEGMENTS AND SEGMENT DESCRIPTORS
,
h
SEGMENT
LIMIT
SEGMENT
BASE
G3010B
Segments are the basic units of 80286 memory management. In contrast to schemes based
on
fixed-
size pages, segmentation allows for a very efficient implementation of software: variable-length segments
can be tailored to the exact requirements of an application_ Segmentation, moreover,
is
consistent with
the way a programmer naturally deals with his virtual address space: programmers are encouraged to
divide code and data into clearly defined modules and structures which are manipulated
as
consistent
entities. This reduces (minimizes) the potential for virtual memory thrashing_ Segmentation also elimi-
nates the restrictions on data structures that span a page (e.g., a word that crosses page boundaries)_
Each segment within an 80286 system
is
defined
by
an associated segment descriptor, which may
appear in one or more descriptor tables. Its inclusion within a descriptor table represents the presence
of its associated segment within the virtual address space defined
by
that table. Conversely, its ommis-
sion from a descriptor table means that the segment
is
absent from the corresponding address space.
6-7
pcjs.org

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Intel 80286 and is the answer not in the manual?

Intel 80286 Specifications

General IconGeneral
Processor TypeMicroprocessor
Clock Speed6 MHz to 25 MHz
Transistor Count134, 000
Addressable Memory16 MB
Instruction Setx86
Architecturex86
Data Bus Width16-bit
Address Bus Width24-bit
Operating ModesReal mode, Protected mode
Process Technology1.5 µm
Voltage5V
Introduced1982
Package68-pin PGA

Related product manuals