Intel 80286 User Manual

MEMORY MANAGEMENT AND VIRTUAL ADDRESSING
'--------- DESCRIPTOR PRIVILEGE LEVEL
'----------- PRESENT (I-yes)
DATA OR STACK SEGMENT
MSB LSB
ACCESSED
(I-yes)
WRITEABLE (I-yes)
'----- EXPAND DOWN (I-down)
'------ EXECUTABLE (O-no for data)
'------- (indicates segment descriptor)
'--------- DESCRIPTOR PRIVILEGE LEVEL
'-- ________ PRESENT (I-yes)
Figure 6-7. Segment Descriptor Access Bytes
6.6 MEMORY MANAGEMENT REGISTERS
G30108
The Protected Virtual Address Mode features of the 80286 operate at high performance due to exten-
sions to the basic 8086 register set. Figure 6·8 illustrates that portion of the extended register structure
that pertains to memory management. (For a complete summary of all Protected Mode registers, refer
to section 10.1).
6.6.1 Segment Address Translation Registers
Figure 6-8 shows the segment registers CS,DS,ES, and SS. In contrast to their usual representation,
however, these registers are
now depicted as 64-bit registers, each with "visible" and "hidden"
components.
The visible portions of these segment address translation registers are manipulated
by programs exactly
as if they were simply the 16-bit segment registers of Real Address Mode. By loading a segment selec-
tor into one of these registers, the program makes the associated segment one of its four currently
addressable segments.
6-9
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Intel 80286 Specifications

General

Processor Type	Microprocessor
Clock Speed	6 MHz to 25 MHz
Transistor Count	134, 000
Addressable Memory	16 MB
Instruction Set	x86
Architecture	x86
Data Bus Width	16-bit
Address Bus Width	24-bit
Operating Modes	Real mode, Protected mode
Process Technology	1.5 µm
Voltage	5V
Introduced	1982
Package	68-pin PGA