Intel 80286 User Manual

INDEX
NT (Nested Task Flag),
(see Flags)
Numeric Data Processor Instructions, 3-30
OF (Overflow Flag),
(see Flags)
Offset Computation, 2-19
Operands, 2-16, 2-17
OR Instruction, 2-23, 3-10, B-80
OUT/OUTW, 2-23,3-29, 10-6, B-81
OUTS/OUTSB/OUTSW Instruction, 3-29,
4-1, B-82
PF (Parity Flag),
(see Flags)
Pointer,
(see Data Types)
POP Instruction, 3-3, B-83
POPA Instruction, 3-2, 3-5, B-85
POPF Instruction, 3-26, 3-28, B-86
Processor Extension Error (Interrupt 6),
(see Interrupt Handling and Interrupt
Priorities)
Processor Extension Not Available,
(Interrupt 7),
(see Interrupt and Interrupt Priorities)
Processor Extension Segment Overrun
Interrupt (Interrupt 9),
(see Interrupt and Interrupt Priorities)
Protected Mode, 1-2, 1-3,6-1
Protected Virtual Address Mode,
1-2,
Protection Implementation, 7-2 - 7-4
Protection Mechanisms,
1-2, 1-3
PUSH, 2-12, 3-2, B-87
PUSHA, 3-2, 3-3,
B-85
PUSHF, B-89
Real Address Mode, 6-1, 6-2
Register,
Base Architecture Diagram,
2-7
Base Register BX, 2-9, 2-17, 2-19, 2-20,
3-1,3-7,3-8 - 3-10,3-14,3-16,
3-17,3-22,4-7
Flags Register, 2-14, 2-15
General Registers,
2-7
Index Registers DI, SI, 2-9
Overview, 2-7
Pointer Registers BP and SP, 2-9
Segment Registers, 2-8
Status and Control, 2-14
Register Direct Mode, 2-20
Register and Immediate Modes, 2-17
Register Indirect Mode, 2-20
(see Addressing Modes)
Reserved Interrupt Vectors,
(see Interrupt Handling and Interrupt
Priorities)
RESET,
10-7
RCL Instruction, 3-14, 3-15,9-10, B-90
RCR Instruction, 3-15, B-90
REP Prefix, 3-23,4-1,4-2, B-92
REPE Prefix, 3-24, B-92
REPNE Prefix, 3-24, B-92
REPNZ Prefix, 3-24
REPZ Prefix, 3-24
RET Instructon, 2-16, 3-17 - 3-19, B-94
ROL Instruction, 3-13, B-90
ROR Instruction, 3-14, B-90
RPL, 7-13, 8-9, 9-6, 11-3, 11-4
SAL Instruction, 3-11, B-97
SAR Instruction, 3-12, B-97
SBB Instruction, 3-8, B-99
SCAS Instruction, 3-4, 3-24, B-100
SEG (Segment
Override Prefix), 2-19
Segment Address Translation Registers,
6-9 - 6-12
Segment Descriptor, 7-10
-7-12
Segment Overrun Exception (Interrupt 13),
(see Interrupt Handling and Interrupt
Priorities)
Segment Selection, 2-18
SF (Sign Flag),
(see Flags)
SGDT Instruction, 6-12, 10-3, B-I0l
SHL Instruction, 3-11, B-97
SHR Instruction, 3-12
SI Register, 2-7, 2-9, 2-11, 2-14 - 2-17,
2-19,3-17,3-23 - 3-25,
4-1
SmT Instruction, 10-3, B-I0l
Index-5
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Intel 80286 Specifications

General

Processor Type	Microprocessor
Clock Speed	6 MHz to 25 MHz
Transistor Count	134, 000
Addressable Memory	16 MB
Instruction Set	x86
Architecture	x86
Data Bus Width	16-bit
Address Bus Width	24-bit
Operating Modes	Real mode, Protected mode
Process Technology	1.5 µm
Voltage	5V
Introduced	1982
Package	68-pin PGA