Intel 80286

INDEX
Interrupt 7 Processor Extension Not
Available, 5-6, 5-7,9-9
Interrupt 8, Interrupt Table Limit
Too Small, 5-6, 5-7, 9-9, 9-10
Interrupt Vectors, 5-3 - 5-7
Reserved Vectors, 5-5, 5-7
Interrupt Vector Table, 5-3
Interrupts and Exceptions,
(see Interrupt Handling and Interrupt
Priorities)
INTO Detected Overflow (Interrupt 4),
(see Interrupt Handling and Interrupt
Priorities)
INTO Instruction, 2-25, 3-22, B-48
INTR, 5-3, 5-4, 9-1, 9-2, 9-7, 11-7
Invalid opcode (Interrupt 6),
(see Interrupt Handling and Interrupt
Priorities)
10PL (I/O Privilege Level),
(see Flags)
IP Register, 2-8, 3-18, 3-19, 5-4
IRET Instruction, 3-17, 3-19, 3-21, 5-5,
8-5 - 8-8, 9-5 - 9-8,9-14, B-51
JCXZ Instruction, 3-21, B-54, B-55
JMP Instruction, 3-17, 3-18, B-56 - B-58
LAHF Instruction, 3-26, B-59
LAR Instruction, 11-3, B-60
LDS Instruction, 3-25, 5-1, B-61
LDT (Local Descriptor Table), 6-5 - 6-7,
6-10,6-12,7-5 -7-8, 7-17, 8-5, 8-6,
8-8,8-9,9-11 - 9-13, 10-1 - 10-4
LEA Instruction, 3-24,-B-63
LEAVE Instruction, 4-2, 4-6, B-64
LES Instruction, 3-25, 5-1, B-61
LGDT Instruction, 6-12, 10-3, 10-5, B-65
LIDT Instruction, 5-6, 5-7, 10-3, 10-6, B-65
LLDT Instruction, 6-12, 10-3, 10-5, B-66
LMSW Instruction, 10-4, 10-6, B-67
LOCK Prefix, 3-29, B-68
LODS/LODSB/LODSW, 3-24, B-69
LOOP Instruction, 3-4, 3-20, 3-21, B-70
LOOPE Instruction, 3-21, B-70
LOOPNE, 3-21, B-70
LOOPNZ, 3-21, B-70
LSL Instruction, 11-3, B-71
Memory,
Physical Size, 2-1
Segmentation, 2-1
Implied Usage, 2-14
Interpretation in Protected Mode, 2-9,
2-10
Interpretation in Real Mode, 2-9,
5-1 - 5-5
Modularity, 2-1
Virtual Size, 2-1
Memory Addressing Modes, 2-17 - 2-21
Memory Management, 6-1, 7-4
Task Managment, 6-1, 6-2, Chapter 8
Context Switching (Task Switching),
8-5, 8-6
Overview, 6-1
Memory Management Registers,
Chapter 6
Memory Mapped I/O,
(see Input/Output)
Memory Mode, 2-20
Memory Segmentation and Segment
Registers, 2-8 - 2-9
MOV Instructions, 2-17, 2-23, 3-1, B-73
MOVS Instructions, 3-23, B-75
MOVSB Instructions, 3-23, B-75
MOVSW Instruction, 3-23, B-75
MSW Register, 5-7, 8-6, 10-4 - 10-7,
B-67
MUL Instruction, 3-8, B-76
NEG Instruction, 3-9, B-n
NMI (Non maskable Interrupt), 5-6,
9-1 - 9-3, 9-9, 9-10
Nonmaskable (interrupt 2),
(see Interrupt Priorities)
NOP Instruction, 2-16, B-78
NOT Instruction, 3-9, 3-10, B-78
Not Present (Interrupt 11)
(see Interrupt Priorities)
NPX Processor Extension, 3-29 - 3-31
Index-4
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