Intel Arria 10 series User Manual

Module Description
TX PLL The transmitter PLL block provides the serial fast clock to the Transceiver Native
PHY block. For this Intel FPGA HDMI design example, fPLL is used as TX PLL.
IOPLL Reconfiguration IOPLL reconfiguration block facilitates dynamic real-time reconfiguration of PLLs
in Intel FPGAs. This block updates the output clock frequency and PLL bandwidth
in real-time, without reconfiguring the entire FPGA. This blocks runs at 100 MHz
in Intel Arria 10 devices.
Due to IOPLL reconfiguration limitation, apply the Quartus INI
permit_nf_pll_reconfig_out_of_lock=on during the IOPLL
reconfiguration IP generation.
To apply the Quartus INI, include
“permit_nf_pll_reconfig_out_of_lock=on” in the quartus.ini file and
place in the file the Intel Quartus Prime project directory. You should see a
warning message when you edit the IOPLL reconfiguration block
(pll_hdmi_reconfig) in the Quartus Prime software with the INI.
Note:
Without this Quartus INI, IOPLL reconfiguration cannot be completed if
the IOPLL loses lock during reconfiguration.
PIO The parallel input/output (PIO) block functions as control, status and reset
interfaces to or from the CPU sub-system.
Table 9. Transceiver Data Rate and Oversampling Factor for Each TMDS Clock
Frequency Range
TMDS Clock Frequency
(MHz)
TMDS Bit clock Ratio Oversampling Factor Transceiver Data Rate (Mbps)
85–150 1 Not applicable 3400–6000
100–340 0 Not applicable 1000–3400
50–100 0 5 2500–5000
35–50 0 3 1050–1500
30–35 0 4 1200–1400
25–30 0 5 1250–1500
Table 10. Top-Level Common Blocks
Module Description
Transceiver Arbiter This generic functional block prevents transceivers from recalibrating
simultaneously when either RX or TX transceivers within the same physical
channel require reconfiguration. The simultaneous recalibration impacts
applications where RX and TX transceivers within the same channel are assigned
to independent IP implementations.
This transceiver arbiter is an extension to the resolution recommended for
merging simplex TX and simplex RX into the same physical channel. This
transceiver arbiter also assists in merging and arbitrating the Avalon-MM RX and
TX reconfiguration requests targeting simplex RX and TX transceivers within a
channel as the reconfiguration interface port of the transceivers can only be
accessed sequentially.
The interface connection between the transceiver arbiter and TX/RX Native
PHY/PHY Reset Controller blocks in this design example demonstrates a generic
mode that apply for any IP combination using the transceiver arbiter. The
transceiver arbiter is not required when only either RX or TX transceiver is used
in a channel.
The transceiver arbiter identifies the requester of a reconfiguration through its
Avalon-MM reconfiguration interfaces and ensures that the corresponding
tx_reconfig_cal_busy or rx_reconfig_cal_busy is gated accordingly.
continued...
2 Intel FPGA HDMI Design Example Detailed Description
UG-20077 | 2017.11.06
Intel
®
FPGA HDMI Design Example User Guide for Intel
®
Arria 10 Devices
18

Intel Arria 10 series Specifications

General

Family	Arria 10
Manufacturer	Intel
Transceiver Data Rate	Up to 17.4 Gbps
Core Voltage	0.9 V
Process Technology	20 nm
Category	FPGA
Package Options	FBGA
ALMs	42, 720 - 427, 200
Operating Temperature	0°C to +85°C (Commercial), -40°C to +100°C (Industrial), -55°C to +125°C (Extended)