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General| Device Family | MAX 10 |
|---|---|
| Category | FPGA |
| Technology Node | 55 nm |
| Maximum Operating Frequency | Up to 450 MHz |
| Logic Elements | 2, 000 to 50, 000 |
| Power Supply | 1.2V |
| DSP Blocks | Up to 144 18x18 multipliers |
| Voltage Support | 1.2V, 3.3V |
| Configuration | Flash-based |
| Operating Temperature | 0°C to 85°C (commercial), -40°C to 100°C (industrial) |
| Process Technology | Embedded Flash Memory Technology |
Summarizes key benefits and supporting features of MAX 10 devices.
Provides an overview of the device's core technical features and capabilities.
Details on how to order MAX 10 devices, including part numbers and options.
Table detailing the maximum resource counts for different MAX 10 device variants.
Information on I/O pin counts and package types for MAX 10 devices.
Guidance on migrating designs between different MAX 10 device densities.
Specifics on I/O migration paths across MAX 10 devices and packages.
Specifics on ADC migration paths across MAX 10 devices and packages.
Explanation of the fundamental logic units (LEs and LABs) in the architecture.
Details on the integrated Analog-to-Digital Converters (ADCs) and their features.
Information on the on-chip non-volatile user flash memory (UFM) capabilities.
Features related to embedded multipliers and Digital Signal Processing (DSP).
Description of the M9K embedded memory blocks and their configuration options.
Details on clocking resources, global clock networks, and Phase-Locked Loops (PLLs).
Information on the programmable general-purpose I/O features and flexibility.
Description of the external memory interface capabilities, including supported standards.
Overview of device configuration features, security, and data compression.
Details on power management options, advantages, and controller schemes.
History of changes and updates made to the MAX 10 FPGA Device Overview document.
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