Intel MAX 10 FPGA User Manual

1.6.1 MAX 10 I/O Vertical Migration Support
Figure 2. Migration Capability Across MAX 10 Devices
• The arrows indicate the migration paths. The devices included in each vertical
migration path are shaded. Some packages have several migration paths. Devices
with lesser I/O resources in the same path have lighter shades.
• To achieve the full I/O migration across product lines in the same migration path,
restrict I/Os usage to match the product line with the lowest I/O count.
Device
Package
V36 V81 M153 U169 U324 F256 E144 F484 F672
10M02
10M04
10M08
10M16
10M25
10M40
10M50
Note: To verify the pin migration compatibility, use the Pin Migration View window in the
Quartus Prime software Pin Planner.
1.6.2 MAX 10 ADC Vertical Migration Support
Figure 3. ADC Vertical Migration Across MAX 10 Devices
The arrows indicate the ADC migration paths. The devices included in each vertical
migration path are shaded.
Device
Package
M153 U169 U324 F256 E144 F484 F672
10M04
10M08
10M16
10M25
10M40
10M50
Dual ADC Device: Each ADC (ADC1 and ADC2) supports 1 dedicated analog input pin and 8 dual function pins.
Single ADC Device: Single ADC that supports 1 dedicated analog input pin and 16 dual function pins.
Single ADC Device: Single ADC that supports 1 dedicated analog input pin and 8 dual function pins.
1 MAX
®
10 FPGA Device Overview
MAX 10 FPGA Device Overview
8

Intel MAX 10 FPGA Specifications

General

Brand	Intel
Model	MAX 10 FPGA
Category	Motherboard
Language	English