Intel MAX 10 FPGA User Manual

Table 7. Pin Migration Conditions for ADC Migration
Source Target Migratable Pins
Single ADC device Single ADC device You can migrate all ADC input pins
Dual ADC device Dual ADC device
Single ADC device Dual ADC device • One dedicated analog input pin.
• Eight dual function pins from the ADC1 block of the
source device to the ADC1 block of the target device.
Dual ADC device Single ADC device
1.7 Logic Elements and Logic Array Blocks
The LAB consists of 16 logic elements (LE) and a LAB-wide control block. An LE is the
smallest unit of logic in the MAX 10 device architecture. Each LE has four inputs, a
four-input look-up table (LUT), a register, and output logic. The four-input LUT is a
function generator that can implement any function with four variables.
Figure 4. MAX 10 Device Family LEs
Row, Column,
And Direct Link
Routing
data 1
data 2
data 3
data 4
labclr1
labclr2
Chip-Wide
Reset
(DEV_CLRn)
labclk1
labclk2
labclkena1
labclkena2
LE Carry-In
LAB-Wide
Synchronous
Load
LAB-Wide
Synchronous
Clear
Row, Column,
And Direct Link
Routing
Local
Routing
Register Chain
Output
Register Bypass
Programmable
Register
Register Chain
Routing from
previous LE
LE Carry-Out
Register Feedback
Synchronous
Load and
Clear Logic
Carry
Chain
Look-Up Table
(LUT)
Asynchronous
Clear Logic
Clock &
Clock Enable
Select
D
Q
ENA
CLRN
1.8 Analog-to-Digital Converter
MAX 10 devices feature up to two ADCs. You can use the ADCs to monitor many
different signals, including on-chip temperature.
1 MAX
®
10 FPGA Device Overview
MAX 10 FPGA Device Overview
9

Intel MAX 10 FPGA Specifications

General

Device Family	MAX 10
Category	FPGA
Technology Node	55 nm
Maximum Operating Frequency	Up to 450 MHz
Logic Elements	2, 000 to 50, 000
Power Supply	1.2V
DSP Blocks	Up to 144 18x18 multipliers
Voltage Support	1.2V, 3.3V
Configuration	Flash-based
Operating Temperature	0°C to 85°C (commercial), -40°C to 100°C (industrial)
Process Technology	Embedded Flash Memory Technology

Summary

MAX 10 FPGA Device Overview

Key Advantages of MAX 10 Devices

Summarizes key benefits and supporting features of MAX 10 devices.

Summary of MAX 10 Device Features

Provides an overview of the device's core technical features and capabilities.

MAX 10 Device Ordering Information

Details on how to order MAX 10 devices, including part numbers and options.

MAX 10 Device Maximum Resources

Table detailing the maximum resource counts for different MAX 10 device variants.

MAX 10 Devices I/O Resources Per Package

Information on I/O pin counts and package types for MAX 10 devices.

MAX 10 Vertical Migration Support

Guidance on migrating designs between different MAX 10 device densities.

MAX 10 I/O Vertical Migration Support

Specifics on I/O migration paths across MAX 10 devices and packages.

MAX 10 ADC Vertical Migration Support

Specifics on ADC migration paths across MAX 10 devices and packages.

Logic Elements and Logic Array Blocks

Explanation of the fundamental logic units (LEs and LABs) in the architecture.

Analog-to-Digital Converter

Details on the integrated Analog-to-Digital Converters (ADCs) and their features.

User Flash Memory

Information on the on-chip non-volatile user flash memory (UFM) capabilities.

Embedded Multipliers and Digital Signal Processing Support

Features related to embedded multipliers and Digital Signal Processing (DSP).

Embedded Memory Blocks

Description of the M9K embedded memory blocks and their configuration options.

Clocking and PLL

Details on clocking resources, global clock networks, and Phase-Locked Loops (PLLs).

FPGA General Purpose I/O

Information on the programmable general-purpose I/O features and flexibility.

External Memory Interface

Description of the external memory interface capabilities, including supported standards.

Configuration

Overview of device configuration features, security, and data compression.

Power Management

Details on power management options, advantages, and controller schemes.

Document Revision History for MAX 10 FPGA Device Overview

History of changes and updates made to the MAX 10 FPGA Device Overview document.