Intel MAX 10 FPGA User Manual

• DSP IP cores:
— Common DSP processing functions such as finite impulse response (FIR), fast
Fourier transform (FFT), and numerically controlled oscillator (NCO) functions
— Suites of common video and image processing functions
• Complete reference designs for end-market applications
• DSP Builder for Intel FPGAs interface tool between the Quartus Prime software and
the MathWorks Simulink and MATLAB design environments
• DSP development kits
1.11 Embedded Memory Blocks
The embedded memory structure consists of M9K memory blocks columns. Each M9K
memory block of a MAX 10 device provides 9 Kb of on-chip memory capable of
operating at up to 284 MHz. The embedded memory structure consists of M9K
memory blocks columns. Each M9K memory block of a MAX 10 device provides 9 Kb of
on-chip memory. You can cascade the memory blocks to form wider or deeper logic
structures.
You can configure the M9K memory blocks as RAM, FIFO buffers, or ROM.
The MAX 10 device memory blocks are optimized for applications such as high
throughput packet processing, embedded processor program, and embedded data
storage.
Table 10. M9K Operation Modes and Port Widths
Operation Modes Port Widths
Single port ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
Simple dual port ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
True dual port ×1, ×2, ×4, ×8, ×9, ×16, and ×18
1.12 Clocking and PLL
MAX 10 devices offer the following resources: global clock (GCLK) networks and
phase-locked loops (PLLs) with a 116-MHz built-in oscillator.
MAX 10 devices support up to 20 global clock (GCLK) networks with operating
frequency up to 450 MHz. The GCLK networks have high drive strength and low skew.
The PLLs provide robust clock management and synthesis for device clock
management, external system clock management, and I/O interface clocking. The
high precision and low jitter PLLs offers the following features:
• Reduction in the number of oscillators required on the board
• Reduction in the device clock pins through multiple clock frequency synthesis from
a single reference clock source
• Frequency synthesis
• On-chip clock de-skew
• Jitter attenuation
• Dynamic phase-shift
1 MAX
®
10 FPGA Device Overview
MAX 10 FPGA Device Overview
11

Intel MAX 10 FPGA Specifications

General

Brand	Intel
Model	MAX 10 FPGA
Category	Motherboard
Language	English