Date Version Changes
• Added a link for workaround to avoid jitter of PLL cascading or non-
dedicated clock paths for Intel Arria 10 PLL reference clock.
• Added a note that you cannot use a transceiver RX pin as a CDR reflk for
HDMI RX or as a TX PLL refclk for HDMI TX.
•
Added a note about how to add set_max_skew constraint for designs
that use TX PMA and PCS bonding.
May 2017 2017.05.08 • Rebranded as Intel.
• Changed part number.
• Updated the directory structure:
— Added hdr files.
—
Changed qsys_vip_passthrough.qsys to nios.qsys.
— Added files designated for Intel Quartus Prime Pro Edition.
• Updated information that the RX-TX Link block also performs external
filtering on the High Dynamic Range (HDR) Infoframe from the HDMI RX
auxiliary data and inserts an example HDR Infoframe to the auxiliary data
of the HDMI TX through Avalon ST multiplexer.
• Added a note for the Transceiver Native PHY description that to meet the
HDMI TX inter-channel skew requirement, you need to set the TX channel
bonding mode option in the Arria 10 Transceiver Native PHY parameter
editor to PMA and PCS bonding.
•
Updated description for os and measure signals.
• Modified the oversampling factor for different transceiver data rate at each
TMDS clock frequency range to support TX FPLL direct clock scheme.
• Changed TX IOPLL to TX FPLL cascade clocking scheme to TX FPLL direct
scheme.
• Added TX PMA reconfiguration signals.
• Edited USER_LED[7] oversampling status. 1 indicates oversampled (data
rate < 1,000 Mbps in Arria 10 device).
• Updated HDMI Design Example Supported Simulators table. VHDL not
supported for NCSim.
• Added link to archived version of the Arria 10 HDMI IP Core Design
Example User Guide.
October 2016 2016.10.31 Initial release.
B Revision History for Intel FPGA HDMI Design Example User Guide for Intel Arria 10 Devices
UG-20077 | 2017.11.06
Intel
®
FPGA HDMI Design Example User Guide for Intel
®
Arria 10 Devices
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