Intel P4000 - DATASHEET REV 001 - Page 5

Datasheet 5
6.7 DMI................................................................................................................. 77
6.8 PLL Signals....................................................................................................... 77
6.9 TAP Signals ...................................................................................................... 78
6.10 Error and Thermal Protection .............................................................................. 79
6.11 Power Sequencing ............................................................................................. 80
6.12 Processor Power Signals ..................................................................................... 81
6.13 Ground and NCTF .............................................................................................. 83
6.14 Processor Internal Pull Up/Pull Down.................................................................... 83
7 Electrical Specifications........................................................................................... 85
7.1 Power and Ground Pins ...................................................................................... 85
7.2 Decoupling Guidelines........................................................................................ 85
7.2.1 Voltage Rail Decoupling........................................................................... 85
7.3 Processor Clocking (BCLK, BCLK#) ...................................................................... 85
7.3.1 PLL Power Supply ................................................................................... 86
7.4 Voltage Identification (VID) ................................................................................ 86
7.5 Reserved or Unused Signals................................................................................ 90
7.6 Signal Groups ................................................................................................... 91
7.7 Test Access Port (TAP) Connection....................................................................... 93
7.8 Absolute Maximum and Minimum Ratings ............................................................. 94
7.9 Storage Conditions Specifications ........................................................................ 94
7.10 DC Specifications............................................................................................... 95
7.10.1 Voltage and Current Specifications............................................................ 96
7.11 Platform Environmental Control Interface (PECI) DC Specifications......................... 103
7.11.1 DC Characteristics ................................................................................ 103
7.11.2 Input Device Hysteresis......................................................................... 104
8 Processor Pin and Signal Information.................................................................... 105
8.1 Processor Pin Assignments................................................................................ 105
8.2 Package Mechanical Information........................................................................ 179
Figures
Figure 1-1 Intel® Celeron™ P4000 and U3000 mobile processor series on the Calpella
Platform................................................................................................ 10
Figure 2-2 Intel Flex Memory Technology Operation ................................................... 22
Figure 2-3 Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes. 23
Figure 2-4 PCI Express Layering Diagram ................................................................. 25
Figure 2-5 Packet Flow through the Layers ................................................................ 26
Figure 2-6 PCI Express Related Register Structures in the Processor ............................. 27
Figure 2-7 Integrated Graphics Controller Unit Block Diagram...................................... 29
Figure 2-8 Processor Display Block Diagram .............................................................. 32
Figure 4-9 Idle Power Management Breakdown of the Processor Cores.......................... 42
Figure 4-10 Thread and Core C-State Entry and Exit .................................................... 42
Figure 4-11 Package C-State Entry and Exit ................................................................ 47
Figure 5-12 Frequency and Voltage Ordering............................................................... 60
Figure 7-13 Active V
CC
and I
CC
Loadline (PSI# Asserted) .............................................. 97
Figure 7-14 Active V
CC
and I
CC
Loadline (PSI# Not Asserted) ........................................ 97
Figure 7-15 VAXG/IAXG Static and Ripple Voltage Regulation ........................................ 99
Figure 7-16 Input Device Hysteresis......................................................................... 104
Figure 8-17 Socket-G (rPGA988A) Pinmap (Top View, Upper-Left Quadrant).................. 106
Figure 8-18 Socket-G (rPGA988A) Pinmap (Top View, Upper-Right Quadrant)................ 107