Intel P4000 - DATASHEET REV 001 - Page 6

6 Datasheet
Figure 8-19 Socket-G (rPGA988A) Pinmap (Top View, Lower-Left Quadrant) .................. 108
Figure 8-20 Socket-G (rPGA988A) Pinmap (Top View, Lower-Right Quadrant) ................ 109
Figure 8-21 BGA1288 Ballmap (Top View, Upper-Left Quadrant) ..................................138
Figure 8-22 BGA1288 Ballmap (Top View, Upper-Right Quadrant) ................................139
Figure 8-23 BGA1288 Ballmap (Top View, Lower-Left Quadrant) ..................................140
Figure 8-24 BGA1288 Ballmap (Top View, Lower-Right Quadrant) ................................ 141
Figure 8-25 rPGA Mechanical Package (Sheet 1 of 2) ................................................. 179
Figure 8-26 rPGA Mechanical Package (Sheet 2 of 2) .................................................. 180
Figure 8-27 BGA Mechanical Package (Sheet 2 of 2) ...................................................181
Tables
Table 2-1 Supported SO-DIMM Module Configurations1..............................................20
Table 2-2 DDR3 System Memory Timing Support ......................................................21
Table 2-3 eDP/PEG Ball Mapping .............................................................................33
Table 2-4 Processor Reference Clocks ......................................................................35
Table 4-5 System States........................................................................................38
Table 4-6 Processor Core/Package State Support ......................................................38
Table 4-7 Integrated Memory Controller States.........................................................39
Table 4-8 PCIe Link States .....................................................................................39
Table 4-9 DMI States ............................................................................................39
Table 4-10 Integrated Graphics Controller States ........................................................39
Table 4-11 G, S and C State Combinations.................................................................40
Table 4-12 D, S, and C State Combination .................................................................40
Table 4-13 Coordination of Thread Power States at the Core Level ................................43
Table 4-14 P_LVLx to MWAIT Conversion ...................................................................43
Table 4-15 Coordination of Core Power States at the Package Level...............................46
Table 4-16 Targeted Memory State Conditions............................................................50
Table 5-17 Intel Celeron P4000 mobile processor series Dual-Core SV Thermal Power
Specifications .........................................................................................56
Table 5-18 18 W Ultra Low Voltage (ULV) Processor Idle Power ....................................56
Table 5-19 35 W Standard Voltage (SV) Processor Idle Power.......................................57
Table 6-20 Signal Description Buffer Types ................................................................70
Table 6-21 Memory Channel A..................................................................................71
Table 6-22 Memory Channel B..................................................................................72
Table 6-23 Memory Reference and Compensation .......................................................73
Table 6-24 Reset and Miscellaneous Signals ...............................................................74
Table 6-25 PCI Express Graphics Interface Signals ......................................................75
Table 6-26 Intel® Flexible Display Interface...............................................................76
Table 6-27 DMI - Processor to PCH Serial Interface .....................................................77
Table 6-28 PLL Signals ............................................................................................77
Table 6-29 TAP Signals............................................................................................78
Table 6-30 Error and Thermal Protection....................................................................79
Table 6-31 Power Sequencing ..................................................................................80
Table 6-32 Processor Power Signals ..........................................................................81
Table 6-33 Ground and NCTF ...................................................................................83
Table 6-34 Processor Internal Pull Up/Pull Down .........................................................83
Table 7-35 Voltage Identification Definition ................................................................86
Table 7-36 Market Segment Selection Truth Table for MSID[2:0] ..................................90
Table 7-37 Signal Groups1.......................................................................................91
Table 7-38 Processor Absolute Minimum and Maximum Ratings ....................................94
Table 7-39 Storage Condition Ratings........................................................................95