Jackson Labs LC_XO - Page 15

© 2012 Jackson Labs Technologies, Inc. 7
LC_XO GPSDO User Manual
Table 2.1 shows the LC_XO board revision 1.0 hardware pin description
Table 2.1 LC_XO board hardware connectors
Pin Name Function
Specification
1 GND GND GND
2 10MHz Out 10MHz output 5V CMOS, <1ns rise time
3 LOCK_OK LOCK
EVENT#
indicator
3.3V: Unit is locked and no
events are pending
0V: Events are pending
4 1PPS OUT 1PPS Output 3.3V CMOS <10ns rise
time
5 1PPS IN 1PPS Input External (optional) 1PPS
Reference Input
6 +5V Out +5V Output 5V +/-5%, <100mA output
from internal DC-DC
switcher. Bypass with
optional 33uF or more for
improved phase noise
7 GND GND GND
8 +3.3Vdd +3.3V Power
Supply
+3.3V, +/-5%, <160mA.
Bypass with optional 10uF
or more for lower noise.
9 GND GND GND
10 ANT IN Antenna Input L1 1574MHz, 5V, 0dB to
50dB antenna gain
11 GND GND GND
12 NMEA Out GPS Raw
NMEA Output
3.3V CMOS, GPS receiver
raw NMEA and
uBlox-binary serial strings
13 ISP# Enable ISP
Mode
Pull to ground during
power-on to enable In
System Flash programming
mode (ISP)