JETWAY PM2M - Pci Timing Settings; Integrated Peripherals

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CMOS Setup Utility – Copyright(C) 1984-2004 Award Software
AGP Timing Settings
Item Help
AGP Share Memory Size 32M
AGP Aperture Size 64M
AGP Master 1 WS Write Enabled
AGP Master 1 WS Read Enabled
CPU to AGP Post Write Enabled
AGP Delay Transaction Enabled
Menu Level >>
↑↓→←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
Note: Change these settings only if you are familiar with the chipset.
3-6-3 PCI Timing Settings
CMOS Setup Utility – Copyright(C) 1984-2004 Award Software
PCI Timing Settings
Item Help
PCI Master 1 WS Write Disabled
PCI Master 1 WS Read Disabled
CPU to PCI Write Buffer Enabled
PCI Delay Transaction Enabled
Menu Level >>
↑↓→←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
3-7 Integrated Peripherals
CMOS Setup Utility – Copyright(C) 1984-2004 Award Software
Integrated Peripherals
Item Help
> OnChip IDE Function Press Enter
> OnChip Device Function Press Enter
> Onboard Super IO Function Press Enter
Init Display First PCI Slot
Menu Level >
↑↓→←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
OnChip IDE Function