JVC DD-9 A - Page 26

@ MSM4066 .
(Top view)
IN/OUT
SIG A
‘-OUT/IN
de A OeneN
@ MSM4024
(Top view)
INPUT PULSES [17]
@ MSM4051
(Top view)
CHANNEL 4
IN/PUT 6
COMMON OUT/IN
7
CHANNEL
IN/OUT 5
INHIBIT
VEE
Vss
L
CHANNEL
IN/OUT
“ON”
CHANNEL
0
* =Don’t Care
D
DD-9A/B/C/E/J/U
=
Block diagram (1/4)
IN/OUT
OUT/IN
CONTROL
Block diagram
Qi Q2 Q3 Q4 a5 06 Q?
INPUT
°
Qy
Q2
a3
aa
a5]
asl
PULSES O-—— _ 7 -
a1
a2
03
a4
5
“
“4
R
R
R
fg
fea
EF
2
L ee es]
RESET
Block diagram
CHANNEL
IN/OUT
“OD 76543210
— °° 99900
TG
sy
Ao
is
a
eo] tom | every 7a
L
{7}
CONVERTER
1
OF
8
L.gowmon
DECODER Ga
WITH aes
co— INHIBIT
TG}
INHIBIT ©
Vss VEE
No. 4198
Fig.:31
an
@ MSM4053
(Top view)
by
IN/OUT] bx
cy
OUT/IN
cx or cy
IN/OUT cx
INHIBIT
VEE
Vss
OUT/IN
bx or by
OUT/IN
axor ay
ay
] IN/OUT
ax
A
B
Cc
ax,bx,cx
ay, by, cy
* =Don’t Care
@ HD74LS175
(Top view)
NONE
cLearl 1 t—d >So 16 | Vee
oth p—J
Nl Ht
16 | 3 | f 1a] 4d
1 | 4 13] 40
20 | 5 | 12| 30
2 | 6 aa Bo 11} 30
expttden.
a re
2a |7 o* Aa 10] 3a
+
GND] & <4 9 [CLOCK
Block diagram
IN OUT
VoD cy Cx by bx ay ax
§ 999990
{7G}
LOGIC BINARY a
AO—} LEVEL TO OUT IN
CONVERTER 1 OF 2 ax or ay
—___4 DECODER
WITH T
INHIBIT &
TG
KA
LOGIC BINARY
Bo LEVEL TO ee OUTIN
CONVERTER 1 OF 2 Ban OGD:
DECODER |
WITH TG
INHIBIT
+ T
TGEy
LOGIC BINARY :
C o-— LEVEL TO OUT IN
ICONVERTER 10F 2 cx or cy
DECODER
WITH TG
= INHIBIT +
tocic +4
INHIBIT o—4 LEVEL
CONVERTER
Vss VEE
Block diagram
Do -—fp af —— 10
pote
ee
a
Wa pen of 20
| p + cick
|
if 1 OF = 20
DATA Lage
PUTS be: SOUIPUTS
af) ae = > ol oma! 30
bode
Lcur’. = 40 |
| ao lee
lec cent pra a=
ao
crock —{ oJ cunp——> 48
o7-xX Ir
CLEAR
F
Low level
High level
HorL
Move to H from L
Q level before to become
input constant level