JVC DLA-X500RBE - Main CPU and Input FPGA Functional Summary; VP FPGA and PA168 Functional Summary; DD FPGA and DD CPU Functional Summary

(No.PA048<Rev.002>)1-27
(11) 4K Upscaling function
(12) Picture Position
(13) MPC control
(14) LVDS output function
5.6.6 Summary of PA168 (MEMC)
(1) Reception of LDVS signal from VP_FPGA (while e-
shift=On: 74.25 MHZm 4-phase, while e-shift=Off and in
3D: 74.25 MHz 2-phase)
(2) Speed interpolation function
(3) Dejada function
(4) Constant speed pass-through function
(5) 3D decoding function
(6) Transmission and reception of the 3D LR identification sig-
nals
(7) 2D/3D conversion
(8) Frame SW function while e-shift=On
(9) Output the V-by-One signal to DD_FPGA
5.6.7 Summary of DD FPGA
(1) V-by-One signal input from PA168
(2) Keystone distortion correction function
(3) RGB Gain correction function
(4) Pixel position correction function
(5) Horizontal/vertical/reciprocating function
(6) Luminance shading correction function
(7) Shading function
(8) VT Gamma correction function
(9) Dithering function
(10) FRC (Frame Rate Control) function
(11) D-ILA device driving function
(12) Image muting function
5.6.8 Summary of DD CPU
(1) Interactive communication with DD CPU
(2) FAN control
(3) Turning on the lamp and ballast control
(4) Lamp door interlock detection
(5) Control output the DD PWB
(6) Temperature sensor detection