JVC DLA-X500RBE - System Block Diagrams; Board Structure Diagram; Functional Layout Diagram

1-26 (No.PA048<Rev.002>)
5.6 Block diagram
5.6.1 Board structure diagram
5.6.2 Functional layout diagram
5.6.3 Summary of MAIN CPU
(1) Monitoring the condition of start-up process of power sup-
ply unit
(2) Interactive communication with DD CPU
(3) Monitoring errors
• FAN Lock/temperature sensor/lamp cover
• Monitoring the returning signal from the power supply unit
• State of the lens cover
(4) User Control
• Transmission and reception of LAN/RS232C
• Transmission and reception of the infrared remote control
• Operation SW control
(5) Controlling the image processing circuit
• HDMI receiver (ADV7619 x 2 pieces)
• Interactive communication with VP_FPGA CPU
• Controlling the I/F FPGA port
(6) Motor controls
• Lens shift
• Lens focus
• Lens zoom
• Cinema filter
• Lens iris
• Lightening iris
•Front cover
(7) LED indicator control
5.6.4 Summary of InputFPGA
(1) Reception of LVTTL signal from an HDMI receiver
(2) Input SW
(3) Converting HDMI signal level
• Convert frontage to Enhanced (0-255) from Standard/
SuperWhite signal.
(4) Converting HDMI color space
• Convert YUV4:2:2 and YUV4:4:4 to RBG
(5) Test Patteern Generator
(6) LVDS output function
5.6.5 Summary of VP FPGA
(1) Reception of LVDS signal
(2) Scaling process
• IP conversion
• Resolution conversion to 1080p
(3) Aspect switching process
(4) User Gamma correction
(5) Color management (7 axis) function
(6) Color profile function
(7) CSC process, color temperature correction
• color temperature correction for each of the optical set-
ting (lamp output, iris, and color filter)
(8) Generating the OSD characters
• Including the logo display and background color display
• Test pattern display
(9) Keystone distortion correction
(10) Noise reduction (NMR, BNR)
Terminal
Board
Operate
Board
LED/IR
Board
Motor
Board
Lamp
Power
(Ballast)
PROCESSOR PWB
MEMC PWB
DD PWB
V-by-
One
Power
Board
Cover
Board
HDMI
ADV
7619
ADV
7619
HDMI
LVDS
LVDS
I2C
I2C
UARI2C
CMS
CPU
MEMC
CPU
UART
PA168
I/F FPGA
MAIN CPU
VP FPGA
DD FPGA
DD CPU
PROCESSOR PWB
MAIN CPU
OSD[23:0]
LVTTL
48bit
LVDS
IF_FPGA
VP_FPGA
PA168
De-Inter lacer
Scaling
OSD Mix
Keystone
CMS
e-Shift
MechaSFT Drive
MEMC
Frame SW
3D_Decode
DD FPGA
Gamma
Shading
Dither
HDMI Input Level
HDMI Color Speace
Input SW
LVTTL
48bit
LVDS
Normal
Speed
LVDS
Normal
Speed
V by
One
MEMC PWB DD PWB
ADV7619
HDMI Rx
ADV7619
HDMI Rx