JVC GR-DVL155EG - Page 91

HGF
EDCBA
4
5
3
2
1
4-664-65
VTRCPU
TO SYSCON(IC1003)
TO
SRV_TX
TO
(IC1001)
(IC1007)
SYSCON
IF_RX
PHYXTPA
16
20
IC8001
156
82
PHYTPB PHYTPA
226
TO SYSCON
TO CAM.DSP
286
PHYXTPB
185 109 108
AIMCK AIBCK AILRCK TPB- TPA- TPB+ TPA+ AIDAT AODAT
AILRCK AIBCK
246
AIDAT1 AODAT0 AIMCK AIDAT0
248 112
OSC27I
CPUWAIT
XCPURW
XCPUDSTB1
XCPUDSTB0
CPUALE
BRSO0
BRSO3
142DALE
TO
CAM.DSP
d
TO
SYSCON
e
DV_ WATT 66
DRWSEL
DRE
DWE
213
143
212
TO
150
67
DV_RST
ADDT15
VTRCPU
ADDTO0
AD0
64
AD15
XRST
TO
CAM.DSP
c
TO TG
CLK27 38
CAM.DSP
TO
b
TO
CAM.DSP
a
191
255
119
39
INV
INH
BRSI3
BRSI0
117
115
YSI0
YSI3
43
122
OUTH
OUTV
MAIN01
257
193
194
258
YSO3
YSO0
242
Sync Detect
IEE1394
LINK
(ISO/
ASYNC
FIFO)
D-RAM I/F
HOST CPU I/F
(DECK_DSP)
CONV)
(CLOCK
RAM
CONV)
(CLOCK
RAM
CONV)
RAM
(CLOCK
CORE)
RISC
RAM
PROGRAM
AUDIO
(WORK
ID Protect
De-formatting)
(CLOCK
CONV)
RAM
SPA
HSP
HID
TRKREF
FRREF
98
101
243
240
TSR
FRP
RAM
(SUB/AUX)
IC3001(DVMAIN)
RAM)
(VBID DET
VIDEO I/F
(ENC/DET)
RAM)
VLD WORK
COMPRESS
(DCT
,
VLC
OUTER ECC
FORMATTER
(Formatting
INNER ECC
(ENC/DEC)
PWMAUDIO
RECDATA
RECCTL
RECCLK
173
174
100
182
X1401
OSCI
144
158
RXD
OSCO
16
TXD
33
99
108
110
TSR
FRP
SPA
FRP
TSR
TO IC3001
AUDIO_CS
S_SHUT
DATA _O U T
PD_L
CLK_OUT
TO IC3001
153
CLK27SEL
133SRV_CS
SRV_RDY
SRV_RST
RESET
SYS_CLK
READY
MSELECT
SYS_OUT
18
128
SYS_IN
17
3
2
62
49
71VD
EEP_READ
EEP_CLK
EEP_WRITE
46
CAM_VD
TO IC3001
130
151
HID_3
RECH
112
174
145
152
HID
HID
PBH
TO IC3501
TO IC3501
DALE26
57
42
DWE
DRE
DRWSEL
DALE
67
DWE
DRE
DRWSEL
50
ADDT15
ADDT00
7
41
DV_ WAIT
DV_RST
ADDT15
ADDT00
DV_ WAIT
TO IC3001
IC1401(DECKCPU)
167
MONI_CHG
DV IN/OUT
TPB+
TPB-
TPA-
J551
DV
TPA+
TO IC3001
AIDAT
AODAT
AIBCK
AILRCK
AIMCK
AUDIO
TO CAM.DSP
TO
AUDIO
TO
SPA
(TO CAM.DSP)
TO JIG CONN.
(CN105)
(PRE/REC)
48ENV_OUT
RECCADJ
AGC_OUT
AGC_BUFF_OUT
10
REC_GAIN
57
PB_MONI
REC_CTL
REC_DTA
REC_CTL
12
44
7
MONI_CHG
R_CTL
REC_DATA
REC_CLK 9
REC_CLK
Y1
19
X2
25
X1
20
1F
2S
1S
RECCTL
RECDATA
RECCLK
FSPLLCTL
VTRCPU
TO
HID1
RECH
PBH
HID3
HID3
40
42
41
HID1
REC_H
PB_H
38
Y2
24
IC3501
2F
2
1F
7
3
6
2S
1S
CN110
2F
HEAD
DAAOUT0
DAAOUT1
DISCRI
11
237
106
IC3005
AMP+
AMP-
AMPB
4
1
2
2
4
IC3502
A0~A19 DQ0~DQ15
IC8003
(16M_FLASH
RAM)
9
45
25
29
DSC R/D_DATA
DSC R/D_ADRESS
39
108
7
20
37 37
71
32
31
HDDSC
32
CLKDSC
31
27 27
76
33
23
DSYO7
DSCO0
71
VDDSC
72
72
FLDDSC
3
3
CLK27
59
59
DSC_WKUP
56
56
DSC_CS
51
51
USB_DP_TX
55
55
FLSH_RST
17
17
DSC_CLK
18
18
DSC_DT_OUT
57
57
DSC_DT_IN
15
15
USBDOWN
16
16
DSC_RST
58
58
MXDT_OUT
19
19
CAPT_REQ
20
20
DSC_STS
DSYO0
76
80
DSCO7
80
11 11
USB_DN_RX
15
USBDOWN
15
33
DSCIO0
23
66
DSCIO7
66
70
DSYIO7
70
CN111
DSYIO0
CN8001
176
246
244
188
247
191
190
237
235
172
249
199
212
219
157
125
206
184
135
205
182
127
146
138
204
221
IC8004
TO
IC8003-12PIN
1
3
YIO0
YIO7
CIO0
CIO7
YIN0
YIN7
CIN0
CIN7
CLKIN1
HDIN
VDIN
FID
MXI
CLKIN2
GIO0
GIO18
SCLK1
SDI1
26
28
11
12
FLSH_CE
FLSH_OE
FLSH_WE
RESET
SDO1
GIO13
RESET
GIO16
GIO7
GIO11
USB_DN
USB_DP
FROM
CN8001-55PIN
18
16
39
RAS
WE
UDQM
19
17
15
CS
CAS
LDQM
37
38
CKE
CLK
23
35
A0
A11
2
53
DQ0
DQ15
16
75
23
150
159
51
2
3
49
30
177
201
160
200
193
180
SDRAM_DATA
SDRAM_ADRESS
IC8002
16M
SDRAM
CXO
X8002
48MHz
2
MMC_CLK
5
Data2Host
7
SD/MMC_CS
9
Data2MMC
CN8002
174
173
250
117
SDI3
SCK3
SDO3
GIO20
ARM_D15
ARM_D0
ARM_A19
ARM_A0
EM_CS_O
EM_OE
EM_WE
M48XI
M48XO
SDR_DQ0
SDR_DQ15
SDR_A0
SDR_A11
SDR_CKE
SDR_CLK
SDR_CS
SDR_CAS
SDR_DQMLH
SDR_RAS
SDR_WE
SDR_DQMLL
DSC10
TO
MONITOR
TO
CAM.DSP
TO TG
TO
CN103-7PIN
TO
CN103-6PIN
TO
SYSCON
11
85
9
10
9
12
11
3
4
1
2
CN103 CN551
REAR07
D8001
C8126
R8068
R8029
WITH DSC MODEL
3
5
21
7
6
IC1402
SRV_JTX
SRV_JRX
TO
SYSCON
(IC1007)
TO
JIG CONN.
(IC1001)
2 WITHOUT DSC MODEL
2