JVC RX-DP10VBK - Page 30

RX-DP10VBK/RX-DP10VSL
RX-DP10RSL
1-30
X-Decoder
Address Buffer & Latches
Control Logic
Memory Address
CE#
OE#
WE#
EEPROM
Cell Array
Y-Decoder
I/O Buffers & Data Latches
DQ7~DQ0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
A17
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
AMS- A0
DQ7- DQ0
CE#
OE#
WE#
VDD
Vss
NC
Address Inputs
Data Input/Output
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
To provide memory address. During Sector-Erase AMS-A12 address
lines will select the sector.
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs
are in tri-state when OE# or CE# is high.
To active the device when CE# is low.
To gate the data output buffers.
To control the write operations.
To provide power supply voltage: 3.0-3.6V for SST39LF512/010/020/040
2.7-3.6V for SST39VF512/010/010/040
Unconnected Pins
Symbol FunctionPin name
39VF0207CWHM03 (IC667) : EEPROM
1. Pin layout
3. Pin function
2. Block diagram