Lattice Semiconductor ECP5 Versa - Appendix A. Schematics

17
ECP5 Versa Development Board
®
Appendix A. Schematics
Figure 10. Board Block Design
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
Power Device Power Pins
Programming 3.3V SPI
PCSA
Bank 8
ECP5
Bank 0
Bank 3
FPGA
Bank 6 Bank 7
Bank 1
Bank 2
SERDES
Designator U1 is the FPGA DUT.
PCIe X1 CH#0
CLK5406
REFERENCE
CLOCKS
PCIe RefClk 156.25M OSC
Expansion Port- 3.3V
1.5V 16-Bit DDR3
SERDES D0 RefClk General Clk
2.5V RGMII PHY#1 2.5V RGMII PHY#2
Expansion Port-3.3V
SMA Test CH#3
Expansion Clk
PLL
100.00M DIFF OSC
LED SEGMENT ARRAY
USER DIP SWITCH
USER LEDS
Revision History: Nov 13, 2014 Rev A Final Design JPB March 27, 2015 Rev B Final Design EK
Bank 2 Bank 6,7
Date: Size
Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
B
B
111
Board Block Diagram
ECP5 VERSA Eval Board
B
Friday, August 21, 2015
Date: Size
Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
B
B
111
Board Block Diagram
ECP5 VERSA Eval Board
B
Friday, August 21, 2015
Date: Size
Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
B
B
111
Board Block Diagram
ECP5 VERSA Eval Board
B
Friday, August 21, 2015