5
ECP5 Versa Development Board
Setting the Configuration Mode
The ECP5 device on the ECP5 Versa Development Board supports a variety of configuration modes, including
1149.1 JTAG and Master SPI. Refer to TN1260, ECP5 sysCONFIG Usage Guide. On the PCB version Rev B, use
the CFG Setting Dip Switch SW4 described in Ta bl e 3.
Table 3.
Configuration Mode CFG[2:0] SW4.3 SW4.2 SW4.1
1149.1 JTAG only 000 Down Down Down
Slave SPI 001 Down Down Up
Master SPI 010 Down Up Down
SCM (Slave_Serial) 101 Up Down Up
SCM (Slave_Parallel) 111 Up Up Up
CFG[2:0] Selection – Rev B
Board Programming
Configuration Status Indicators
(See Appendix A, Sheet 3, Figure 12 - Programming)
Figure 3. ECP5 Status LEDs and Push-button Controls
The LEDs indicate the configuration status of the ECP5 FPGA.
• D1
7 (red) illuminated indicates that programming was aborted or reinitialized, driving the INITN output low.
• D20 (green) illuminated indicates the successful completion of configuration by releasing the open collector
DONE output pin.
• D19 (red) illuminated indicates that PROGRAMN is low.
• D18 (red) illuminated indicates that GSRN is low.
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