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Lattice Semiconductor ECP5 Versa - Appendix C. Demo Board Rev a Information; ECP5 Versa Development Board - Working with Revision a; ECP5 Pin Assignment Changes

Lattice Semiconductor ECP5 Versa
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ECP5 Versa Development Board
®
Appendix C. Demo Board Rev A Information
ECP5 Versa Development Board – Working with Revision A
This document covers the Revision B of ECP5 Versa. To work with Revision A there are several items to be aware
of:
Setting the Configuration Mode
On the Rev A, setting the Configuration Mode requires modifying the resistor population in the CFG[2:0] Setting
Re
sistor Field (see Figure 3) as described in Ta ble 3. This requires adding and/or removing 0603 size SMT resis-
tors as necessary. Some soldering skill and the correc
t equipment is necessary to perform this rework.
Figure 20. CFG[2:0] Setting Resistor Field – Revision A
Table 14. CFG[2:0] Selection – Revision A
Rev A
Configuration Mode CFG[2:0]
R190
(1K-4.7 kOhm)
R191
(1K-4.7 kOhm)
R192
(1K-4.7 kOhm)
R182
(0 - 1 kOhm)
R188
(0 - 1 kOhm)
R 1 8 9
(0 - 1 kOhm)
1149.1 JTAG only 000 removed removed removed placed placed placed
Slave SPI 001 removed removed placed placed placed removed
Master SPI 010 removed placed removed placed removed placed
SCM (Slave_Serial) 101 placed removed placed removed placed removed
SCM (Slave_Parallel) 111 placed placed placed removed removed removed
ECP5 Pin Assignment Changes
The following pins (Tabl e 15) have changed assignment between the Rev A and Rev B board. These functions
would need to be remapped for use between the two boards.
Table 15. Pin Assignment Updates - Rev A vs Rev B
Pin Signal / Function Rev A ECP5 Ball Location Rev B ECP5 Ball Location
SEG1 (Character LED) L19 L18
Switch 3-7 J19 K19
Phy1_CLK125 (Ethernet Phy 1) L18 L19
Phy2_RxCLK (Ethernet Phy 2) K19 J19
1. Removing all six resistors is equivalent to Slave Parallel mode due to internal weak Pull-up resistors on CFG[2:0] pins.

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