9
ECP5 Versa Development Board
General Purpose Clock Source
An on-board 100 MHz LVDS oscillator is provided for general purpose use. This clock source is connected to differ-
ential inputs P3 and P4 and must be used as LVDS inputs t
o the FPGA. This pin pair also provides optimal inter-
face to the FPGA PLL for customized use.
The PCI Express add-in card specific
ation requires add-in boards to include capabilities to tell the host of its pres-
ence. The ECP5 Versa Development Board allows this optional connection via a board jumper. Using the board
wit
h a PCI Express host requires the setting shown in Figure 7 below.
Figure 7. PCI Express PRSNT Control Connection
J4
1 2
3 4
5 6
PCI Express PRSNT
Jumper Selector
SERDES
The ECP5 Dual Channel Unit (DCU) SERDES FPGA is utilized on the board for several purposes. DCU0, Channel
0 is provisioned to provide a single, full-duplex PCI Express channel. The high-speed signals are connected to the
PCI Express edge connection. DCU0, Channel 1 is connected to the SMA connectors for external electrical dem-
onstrations.
Table 4. PCI Express Channel Interconnections
Signal Name SERDES Port FPGA Ball Number
PETp0 HDRXP0_D0CH0 Y5
PETn0 HDRXN0_D0CH0 Y6
PERp0 HDTXP0_D0CH0 W4
PERn0 HDTXN0_D0CH0 W5
Table 5. SMA Test Interconnections
Connector SERDES Port FPGA Ball Number
J5 HDRXP0_D0CH1 Y7
J6 HDRXN0_D0CH1 Y8
J7 HDTXP0_D0CH1 W8
J8 HDTXN0_D0CH1 W9
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