23
ECP5 Versa Development Board
Figure 16. DDR3 Memory
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ALL Memory controller
buses, clocks, and contro l
traces must be 50 Ohm
Transmission line s
PLACE CLOSE TO MEMORY CHIP
Place Address/Control Termination Resistors as close as possible to Memory Chip U7
VTT
X1 needs to be matched length
for all traces
U1 Pin
MEMORY DEVICE TERMINATION for ADDRESS/ CONTROL SIGNALS
X1
X2
Termination
at end of line
Memory
Place close to FPGA
Schematic symbols rev 4.1
Schematic symbols rev 4.1
Bank 6
Bank 7
DDR3_A3
DDR3_DQ1
DDR3_DQ4
DDR3_DQ2
DDR3_DQ0
DDR3_DQ5
DDR3_DQ7
DDR3_DQ3
DDR3_DM1
DDR3_VREF
DDR3_A5
DDR3_A3
DDR3_A0
DDR3_A8
DDR3_A4
DDR3_A1
DDR3_A7
DDR3_A6
DDR3_A2
DDR3_A9
DDR3_A10
DDR3_K0
DDR3_K0#
DDR3_A12
DDR3_A11
DDR3_BA2
DDR3_A12
DDR3_BA1
DDR3_RAS#
DDR3_A8
DDR3_A5
DDR3_A2
DDR3_A11
DDR3_SD0
DDR3_CS0#
DDR3_DQ9
DDR3_DQ12
DDR3_DQ14
DDR3_DQ10
DDR3_DQ8
DDR3_DQ13
DDR3_DQ15
DDR3_DQ11
DDR3_VS
DDR3_ODT0
DDR3_RAS#
DDR3_WE#
DDR3_CE0
DDR3_K0#
DDR3_BA0
DDR3_BA1
DDR3_RST#
KOC
DDR3_A4
DDR3_A0
DDR3_A10
DDR3_CAS#
DDR3_A9
DDR3_A1
DDR3_A6
DDR3_DQS0#
DDR3_DQS1#
DDR3_DQS1
DDR3_DQS0
DDR3_A7
DDR3_BA2
DDR3_ODT0
DDR3_DQ6
ZQ0
MEM_VREF
DDR3_DM0
DDR3_CAS#
DDR3_K0
DDR3_BA0
DDR3_WE#
DDR3_CE0
DDR3_CS0#
DDR3_A0
DDR3_A2
DDR3_VREF
MEM_VREF
ECP5_VREF
DDR3_A6
DDR3_A9
DDR3_A3
DDR3_A1
DDR3_A11
DDR3_A4
DDR3_A7
DDR3_A10
DDR3_A12
DDR3_A5
DDR3_BA0
DDR3_BA1
DDR3_BA2
DDR3_CAS#
DDR3_CE0
DDR3_ODT0
DDR3_WE#
DDR3_RAS#
DDR3_DQ3
DDR3_DQ1
DDR3_DQ0
DDR3_DQ4
DDR3_DQ2
DDR3_DQ5
DDR3_DQ7
DDR3_DQ11
DDR3_DQ15
DDR3_DQ10
DDR3_DQ12
DDR3_DM1
DDR3_DQ14
DDR3_DQ8
DDR3_DQ9
DDR3_DQ13
DDR3_DQS0#
DDR3_DQS0
DDR3_RST#
PCLKT0
PCLKC0
SWITCH4
SWITCH3
SWITCH2
SWITCH1
SWITCH[1..8]
SWITCH4
SWITCH3
SWITCH2
SWITCH1
100MHz
100MHz_N
DDR3_K0#
DDR3_K0
100MHz 100MHz_N
ECP5_VREF
DDR3_DM0
DDR3_DQS1#
DDR3_DQS1
DDR3_A8
100MHz_N
100MHz
ECP5_VREF
DDR3_DQ6
DDR3_CS0#
1_5V
1_5V
2_5V
2_5V
DDR3_VTT
DDR3_VTT
DDR3_VDD
1_5V
DDR3_VDDQ
DDR3_VDD
DDR3_VDDQ
1_5V
DDR3_VTT
1_5V
1_5V
1_5V
1_5V
1_5V
3_3V
1_5V
1_5V
1_5V
1_5V
1_5V
1_5V
1_5V
1_5V
PCLKT0 [9]
PCLKC0 [9]
SWITCH[1:8][8]
Date:
Size
Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
C
B
117
DDR3 Memory
ECP5 VERSA Eval Board
B
Friday, August 21, 2015
Date:
Size
Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
C
B
117
DDR3 Memory
ECP5 VERSA Eval Board
B
Friday, August 21, 2015
Date:
Size
Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
C
B
117
DDR3 Memory
ECP5 VERSA Eval Board
B
Friday, August 21, 2015
R145
0R-0603SMT
R1R1
R1=50 Ohm
RP1
CTS-RT1402B7
A2
A2
B2
B2
C2
C2
D2
D2
E2
E2
F2
F2
G2
G2
H2
H2
J2
J2
A3
A3
B3
B3
C3
C3
D3
D3
E3
E3
F3
F3
G3
G3
H3
H3
J3
J3
A1
A1
B1
B1
C1
C1
D1
D1
E1
E1
F1
F1
G1
G1
H1
H1
J1
J1
C241
10NF-0603SMT
R150
50R-0402SMT
C218
100NF-0603SMT
C222
100NF-0603SMT
R149
OPEN-0603SMT
ddr3-96bga
U11B
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC#
N7
BA0
M2
BA1
N8
CAS#
K3
CK
J7
CK#
K7
CKE
K9
CS#
L2
LDM
E7
LDQS
F3
LDQS#
G3
ODT
K1
RAS#
J3
RST#
T2
WE#
L3
ZQ
L8
NC_J1
J1
NC_L1
L1
NC_J9
J9
NC_L9
L9
NC_T3
T3
NC_T7
T7
NC_M7
M7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
UDM
D3
UDQS
C7
UDQS#
B7
BA2
M3
R144
OPEN-0603SMT
C178
1UF-16V-0805SMT
LFE5UM-45F-BG381
U1F
VCCIO7
H6
VCCIO7
H7
VCCIO7
J6
PL11A/ULC_GPLL0T_IN
A4
PL11B/ULC_GPLL0C_IN
A5
PL11C/ULC_GPLL0T_MFGOUT2
B5
PL11D/ULC_GPLL0C_MFGOUT2
C5
PL14A/ULC_GPLL0T_MFGOUT1
C4
PL14B/ULC_GPLL0C_MFGOUT1
B4
PL14C
A3
PL14D
B3
PL17A
E4
PL17B
D5
PL17C
C3
PL17D
D3
PL20A
F4
PL20B
E3
PL20C
E5
PL20D
F5
PL23A
A2
PL23B
B1
PL23C/VREF1_7
B2
PL23D
C2
PL26A
C1
PL26B
D1
PL26C
D2
PL26D
E1
PL29A/GR_PCLK7_1
H4
PL29B
G5
PL29C/GR_PCLK7_0
H5
PL29D
H3
PL32A/PCLKT7_1
G3
PL32B/PCLKC7_1
F3
PL32C/PCLKT7_0
F2
PL32D/PCLKC7_0
E2
C185
100NF-0603SMT
C224
100NF-0603SMT
+
C170
47UF-16V-TANTBSMT
C217
10NF-0603SMT
PP1
12
C200
10NF-0603SMT
FB21
BLM41PG600SN1
C191
100NF-0603SMT
C171
1UF-16V-0805SMT
R156
100R-0402SMT
R154
50R-0402SMT
C187
10NF-0603SMT
C173
1UF-16V-0805SMT
R147
240R-0603SMT
LFE5UM-45F-BG381
U1E
VCCIO6
L6
VCCIO6
L7
VCCIO6
M6
PL35A/PCLKT6_1
G2
PL35B/PCLKC6_1
F1
PL35C/PCLKT6_0
H2
PL35D/PCLKC6_0
G1
PL38A/GR_PCLK6_0
J4
PL38B
J5
PL38C/GR_PCLK6_1
J3
PL38D
K3
PL41A
K2
PL41B
J1
PL41C
H1
PL41D
K1
PL44A
K4
PL44B/VREF1_6
K5
PL44C
L4
PL44D
L5
PL53A
M5
PL59A
M4
PL59B
N5
PL59C/D15/IO15
N4
PL59D/D14/IO14
P5
PL62A/D13/IO13
N3
PL62B/D12/IO12
M3
PL62C/D11/IO11
L3
PL62D/D10/IO10
L2
PL65A/LLC_GPLL0T_MFGOUT2
N2
PL65B/LLC_GPLL0C_MFGOUT2
M1
PL65C/D9/IO9
L1
PL65D/D8/IO8
N1
PL68A/LLC_GPLL0T_MFGOUT1
P1
PL68B/LLC_GPLL0C_MFGOUT1
P2
PL68C/LLC_GPLL0T_IN
P3
PL68D/LLC_GPLL0C_IN
P4
R143
OPEN-0603SMT
R151
50R-0402SMT
C186
100NF-0603SMT
R157
10K-0402SMT
C198
10NF-0603SMT
R153
50R-0402SMT
C205
100NF-0603SMT
C195
100NF-0603SMT
U12
LP2998-SO8
GND
1
SD
2
VSENSE
3
VREF
4
VDDQ
5
AVIN
6
PVIN
7
VTT
8
C188
100NF-0603SMT
C204
10NF-0603SMT
C183
100NF-0603SMT
C196
10NF-0603SMT
C190
10NF-0603SMT
C223
10NF-0603SMT
C206
10NF-0402SMT
C181
1UF-16V-0805SMT
C226
10NF-0603SMT
DI
R148
OPEN-0603SMT
FB23
MPZ1608Y600B
DI
1 2
C225
100NF-0603SMT
DI
C189
100NF-0603SMT
C175
100NF-0603SMT
C182
10NF-0603SMT
+
C177
100UF-D3POSCAP
+
C179
10UF-16V-TANTBSMT
C221
10NF-0603SMT
C203
10NF-0402SMT
12
C174
100NF-0603SMT
R141
0R-0603SMT
C242
100NF-0603SMT
C194
10NF-0603SMT
X1
100_00MHz_LVDS
Q_N
5
Q
4
VCC
6
GND
3
DIS#
1
NC
2
PAD
7
C192
10NF-0603SMT
R146
0R-0603SMT
ddr3-96bga
U11A
VDD
B2
VDD
D9
VDD
K2
VDD
K8
VDD
G7
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VSS
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSSQ
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E8
VREFCA
M8
VDDQ
C9
VDDQ
E9
VDDQ
F1
VDDQ
H9
VREFDQ
H1
VSSQ
F9
VSSQ
G1
VSSQ
G9
VDDQ
D2
VDDQ
H2
VSSQ
E2
FB22
BLM41PG600SN1
R155
50R-0402SMT
R142
4_7K-0603SMT
C220
100NF-0603SMT
C199
100NF-0603SMT
C184
10NF-0603SMT
C202
10NF-0402SMT
C193
100NF-0603SMT
C172
100NF-0603SMT
C201
100NF-0603SMT
C197
100NF-0603SMT
R152
50R-0402SMT
+
C180
22UF-16V-TANTBSMT
+
C176
22UF-16V-TANTBSMT
C219
10NF-0603SMT
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