Programming Cables
User Guide
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FPGA-UG-02042-26.2 11
Notes:
1. For older Lattice ISP devices, a 0.01 μF decoupling capacitor is required on ispEN/ENABLE of the target board.
2. For HW-USBN-2A/2B, the target board supplies the power - Typical ICC = 10 mA. For devices that have a VCCJ pin, the VCCJ must be connected to the cable’s VCC. For other
devices, connect the appropriate bank VCCIO to the cable's VCC. A 0.1 μF decoupling capacitor is required on VCCJ or VCCIO close to the device. Please refer to the device data
sheet to determine if the device has a VCCJ pin or what VCCIO bank governs the target programming port (this may not be the same as a target device’s core VCC/VSS plane).
3. Open drain signals. External pull-up ~2.2 kΩ resistor to the appropriate bank VCCIO or VCCJ is required.
4. When using PAC-Designer® software to program ispPAC or ispClock devices, do not connect TRST/DONE.
5. If using a cable older than HW-USBN-2B, connect a +5 V external supply between iCEprogM1050 pin 4 (VCC) and pin 2 (GND).
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