MachXO2 Programming and Configuration Usage Guide
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The MachXO2 must be in user mode in order to access the WISHBONE interface. Accessing and updating the
resources made available by the configuration logic must be done in Transparent mode. Attempting accesses to
the configuration logic in offline mode causes a deadlock because the MachXO2 leaves user mode.
You can get more detailed information about the MachXO2 WISHBONE interface by reading TN1205, Using User
Flash Memory and Hardened Control Functions in MachXO2 Devices.
JTAG Mode
The JTAG port is the most flexible configuration and programming port available on the MachXO2. The JTAG pro-
vides:
• Offline Flash memory programming
• Transparent Flash memory programming
• Offline SRAM configuration
• Full access to the MachXO2 Configuration Logic
• Device chaining
• IEEE 1149.1 testability
• IEEE 1532 Compliant programming
The JTAG port is available when the MachXO2 is in Feature Row HW Default Mode state (that is, blank/erased).
The port is enabled by default by Diamond 1.4. The MachXO2 JTAG port pins are not dedicated to performing the
IEEE 1149.1 TAP function. The JTAG port may be recovered for use as general purpose I/O. See the sysCONFIG
Pins section for details on recovering the JTAG port pins for use as general purpose I/O.
The MachXO2 JTAG port is a valuable asset due to its flexibility. It provides the best capabilities for system and
device debug. Lattice recommends the JTAG port remain accessible in every MachXO2 design. Advantages for
keeping the JTAG port active include:
• Multi-chain Architectures: The JTAG port is the only configuration and programming port that permits the
MachXO2 to be combined in a chain of other programmable logic.
• Reveal Debug: The Lattice Reveal debug tool is an embed-able logic analyzer tool. It allows you to analyze the
logic inside the MachXO2 in the same fashion as an external logic analyzer permits analysis of board level logic.
Reveal access is only available via the MachXO2 JTAG port.
• SRAM Readback: The JTAG port is the only sysCONFIG port able to directly access the MachXO2’s configura-
tion SRAM. It is occasionally necessary to perform failure analysis for SRAM based FPGAs. A key component to
failure analysis can involve reading the configuration SRAM. This kind of failure analysis is lost when the JTAG
port is not enabled.
• Boundary Scan Testability: Board level connectivity testing performed using IEEE 1149.1 JTAG is a key capa-
bility for assuring the quality of assembled printed-circuit-boards. Preserving the MachXO2 JTAG port is vital for
boundary scan testability. Lattice provides Boundary Scan Description Language files for the MachXO2 on the
Lattice website.
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