MachXO2 Programming and Configuration Usage Guide
3
Configuration Process and Flow
Prior to becoming operational, the FPGA goes through a sequence of states, including initialization, configuration
and wake-up.
Figure 1. Configuration Flow
The MachXO2 sysCONFIG ports provide industry standard communication protocols for programming and config-
uring the FPGA. Each of the protocols shown in Table 1 provides a way to access the MachXO2 device’s internal
Flash memory, or to load its configuration SRAM. The Memory Space Accessibility section provides information
about the capabilities of each sysCONFIG port.
The sysCONFIG ports capable of accessing the Flash memory have a priority order. Table 1 lists each of the sys-
CONFIG ports in their priority order. The MSPI configuration port does not have the ability to alter the Flash mem-
ory space, and as a result is not a factor in the sysCONFIG port priority scheme. The priority scheme is important
to be aware of, as a Configuration Logic operation using a low priority sysCONFIG port can be interrupted by a
higher priority sysCONFIG port. The operation of the Configuration Logic is not defined when a low priority sys-
CONFIG port is interrupted by a higher priority sysCONFIG port. Do not permit simultaneous access to the Config-
uration Logic using a sysCONFIG port.
Power not stable
PROGRAMN or
INITN=Low
INITN=Low
User Mode
Configuration
Write SRAM Memory
ERROR
Power Up
VCC > 1.06V or
VCC > 2.1V (HC devices)
VCCIO > 1.06V
INITN and DONE
Driven Low
Initialization
Wake Up
DONE Released
INITN Released
Device refresh
Device refresh
Device refresh
Device refresh:
• PROGRAMN falling edge
• IEEE 1532 REFRESH command
PROGRAMN de-asserted and t
INITL
expired
All configuration data received
To Next Page
Loading...
