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Lattice Semiconductor MachXO2 User Manual
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MachXO2 and MachXO3 Starter Kit
Evaluation Board User Guide
FPGA-
EB
-02036-1.4
January 2022
2
Table of Contents
Table of Contents
3
Acronyms in this Document
5
Introduction
6
Features
7
Figure 2.1. Machxo3 Board (Machxo3L Version), Top Side
7
Figure 2.2. Machxo3 Board (Machxo3L Version), Bottom Side
8
Storage Handling
9
Software Requirements
10
Machxo2 and Machxo3 Devices
11
Demonstration Design
12
Overview
12
Figure 7.1. Machxo2 and Machxo3L/Lf-6900C Block Diagram
12
Run the Demonstration Design
13
Figure 6.1. Demonstration Design Block Diagram
13
Table 7.1. Starter Kit Components and Interfaces
13
Table 6.1. DIP Switch and LED Behavior
14
Download Demo Designs
15
Programming a Demo Design with the Lattice Diamond Programmer
15
Machxo2 and Machxo3 Starter Kits
17
Subsystems
17
Clock Sources
17
Expansion Header Landings
17
Table 7.2. Expansion Connector Reference
17
Table 7.3. Expansion Header Pin Information (J3)
18
Table 7.4. Expansion Header Pin Information (J4)
19
Table 7.5. Expansion Header Pin Information (J6)
20
Table 7.6. Expansion Header Pin Information (J8)
21
Figure 7.2. J3/J4 Header Landing Callout
22
Figure 7.3. J6/J8 Header Landing Callout
22
Machxo2/Machxo3 FPGA
23
Programming Interface Circuits
23
Figure 7.4. J1 Header Landing and LED Array Callout
23
Table 7.7. Machxo2 and Machxo3 FPGA Interface Reference
23
Table 7.8. USB/JTAG Interface Reference
23
Leds
24
Power Supply
24
Test Points
24
USB Programming and Debug Interface
24
Table 7.9. JTAG Programming Pin Information
24
Table 7.10. SPI Programming Pin Information
24
Table 7.11. I 2 C Programming Pin Information
24
Table 7.12. Power and User Leds Reference
24
Board Modifications
25
Bypassing the USB Programming Interface
25
Applying External Power
25
Measuring Bank and Core Power
25
Mechanical Specifications
25
Environmental Requirements
25
Table 7.13. USB Interface Reference
25
Troubleshooting
26
Leds Do Not Flash
26
USB Cable Not Detected
26
Accessing the Troubleshooting the USB Driver Installation Guide
26
Restoring Original Demo Design
26
Ordering Information
27
Table 9.1. Ordering Information
27
Technical Support Assistance
28
Appendix A. Schematic Diagrams
29
Figure A.1. Block Diagram
29
Figure A.2. USB Interface to JTAG
30
Figure A.3. FPGA
31
Figure A.4. FPGA
32
Figure A.5. Power Leds
33
Figure A.6. Bank 2 I/O
34
Figure A.7. Bank 3, 4, 5 I/O
35
Figure A.8. Power Decoupling and Leds
36
Appendix B. Bill of Materials
37
Revision History
39
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Lattice Semiconductor MachXO2 Specifications
General
Brand
Lattice Semiconductor
Model
MachXO2
Category
Controller
Language
English
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